參數(shù)資料
型號： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機控制器接口
文件頁數(shù)： 145/152頁
文件大?。?/td> 1625K
代理商： FW323
Agere Systems Inc.
145
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Internal Register Configuration
(continued)
PHY Core Register Fields for Cable Environment
Table 129. PHY Core Register Fields for Cable Environment
Field
Size
Type
Power Reset
Value
000000
Description
Physical_ID
6
R
The address of this node is determined during self-identification. A
value of 63 indicates a malconfigured bus; the link will not transmit
any packets.
When set to one, indicates that this node is the root.
Cable power active.
Root hold-off bit. When set to one, the force_root variable is TRUE,
which instructs the PHY core to attempt to become the root during
the next tree identify process.
Initiate bus reset. When set to one, instructs the PHY core to set ibr
TRUE and reset_time to RESET_TIME. These values in turn cause
the PHY core to initiate a bus reset without arbitration; the reset
signal is asserted for 166
μ
s. This bit is self-clearing.
Used to configure the arbitration timer setting in order to optimize
gap times according to the topology of the bus. See Section 4.3.6
of IEEE Standard 1394-1995 for the encoding of this field.
This field has a constant value of seven, which indicates the
extended PHY core register map.
The number of ports implemented by this PHY core. This count
reflects the number.
Indicates the speed(s) this PHY core supports:
R
PS
RHB
1
1
1
R
R
0
—
0
RW
IBR
1
RW
0
Gap_count
6
RW
3F
16
Extended
3
R
7
Total_ports
4
R
3
Max_speed
3
R
010
2
000
2
= 98.304 Mbits/s.
001
2
= 98.304 and 196.608 Mbits/s.
010
2
= 98.304, 196.608, and 393.216 Mbits/s.
011
2
= 98.304, 196.608, 393.216, and 786.43 Mbits/s.
100
2
= 98.304, 196.608, 393.216, 786.432, and
1,572.864 Mbits/s.
101
2
= 98.304, 196.608, 393.216, 786.432, 1,572.864, and
3,145.728 Mbits/s.
All other values are reserved for future definition.
Worst-case repeater delay, expressed as 144 + (delay * 20) ns.
Link Active.
Cleared or set by software to control the value of the L
bit transmitted in the node’s self-ID packet 0, which will be the logi-
cal AND of this bit and LPS active.
See description Cleared or set by software to control the value of the C bit transmit-
ted in the self-ID packet. Powerup reset value is set by
CONTENDER pin.
000
The difference between the fastest and slowest repeater data
delay, expressed as (jitter + 1) * 20 ns.
See description
Power-Class.
Controls the value of the pwr field transmitted in the
self-ID packet. See Section 4.3.4.1 of IEEEStandard 1394-1995 for
the encoding of this field. PC0, PC1, and PC2 pins set up power
reset value.
Delay
LCtrl
4
1
R
0000
1
RW
Contender
1
RW
Jitter
3
R
Pwr_class
3
RW
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