參數(shù)資料
型號(hào)： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口
文件頁數(shù)： 140/152頁
文件大?。?/td> 1625K
代理商： FW323
140
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Electrical Characteristics
(continued)
Table 123. Driver Characteristics
Table 124. Device Characteristics
Parameter
Test Conditions
56
load
Drivers disabled
Driver enabled,
speed signaling off*
200 Mbits/s speed
signaling enabled
400 Mbits/s speed
signaling enabled
Symbol
V
OD
V
OFF
I
DIFF
Min
172
—
1.05
Typ
—
—
—
Max
265
20
1.05
Unit
mV
mV
mA
Differential Output Voltage
Off-state Common-mode Voltage
Driver Differential Current,
TPA+, TPA
, TPB+, TPB
Common-mode Speed Signaling
Current, TPB+, TPB
* Limits are defined as the algebraic sum of TPA+ and TPA
driver currents. Limits also apply to TPB+ and TPB
as the algebraic sum of driver
currents.
Limits are defined as the absolute limit of each of TPB+ and TPB
driver currents.
I
SP
2.53
—
4.84
mA
I
SP
8.1
—
12.4
mA
Parameter
Test Conditions
V
DD
= 3.3 V
Symbol
I
DD
Min
Typ
Max
Unit
Supply Current:
D0, 3 Ports Active
Cycle Starts on Bus
D0, 2 Ports Active
Cycle Starts on Bus
D0, 1 Port Active
Cycle Starts on Bus
D1, LPS On, Link Ready, 1 Port
Active, PCI Clock Off (or Very
Slow) Wake-up is Possible from
This State
D2, LPS Off, PCI Clock Off (or
Slow), Ports Suspended, PHY
Core Off, Wake-up is Possible
from This State
D3Hot, LPS Off, PCI Clock Off
(or Slow), Ports Disabled, PHY
Core Off, Wake-up is Possible
from This State
D3Cold, Power is Removed from
Chip, No Wake-up is Possible
from This State
High-level Output Voltage
Low-level Output Voltage
High-level Input Voltage
Low-level Input Voltage
Pull-up Current,
RESETN Input
—
—
—
—
—
—
—
158
140
122
86
<1
<1
0
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
I
OH
max, V
DD
= min
I
OL
min, V
DD
= max
CMOS inputs
CMOS inputs
V
I
= 0 V
V
OH
V
OL
V
IH
V
IL
I
I
V
DD
– 0.4
—
0.7V
DD
—
11
—
—
—
—
—
—
0.4
—
V
V
V
V
μ
A
0.2V
DD
32
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