參數(shù)資料
型號： FTS64K
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： 50/MDR/RECP/VERT PRS FIT/M2.6/SCW/30 MIN
中文描述： 64K的快閃記憶體字節(jié)
文件頁數(shù)： 41/44頁
文件大小： 401K
代理商： FTS64K
41
Section 6 Interrupts
6.1 General
The FTS64K module can generate an interrupt when all Flash commands are completed or the address,
data and command buffers are empty.
Table 6-1 Flash Interrupt Sources
NOTE
Vector addresses and their relative interrupt priority are determined at the MCU level
6.2 Description of Interrupt Operation
Figure 6-1
shows the logic used for generating interrupts.
This system uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to
discriminate for the interrupt generation.
Interrupt Source
Interrupt Flag
Local Enable
Global(CCR)
Mask
Flash Address, Data and
Command Buffers empty
CBEIF
(FSTAT from any Flash block)
CBEIE
I Bit
All Commands are
completed on Flash
CCIF
(FSTAT from any Flash block)
CCIE
I Bit
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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