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| 型號： | FTS64K |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 50/MDR/RECP/VERT PRS FIT/M2.6/SCW/30 MIN |
| 中文描述： | 64K的快閃記憶體字節(jié) |
| 文件頁數(shù)： | 15/44頁 |
| 文件大小： | 401K |
| 代理商： | FTS64K |
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FTS64K Block User Guide — Version V01.00
15
Section 3 Memory Map and Registers
3.1 Overview
This section describes the FTS64K memory maps and registers.
3.2 Modules Memory Map
Figure 3-1
showstheFTS64Kmemorymap.TheSTAR12architectureplacestheFlashmemoryaddress
between $4000 and $FFFF, which corresponds to three 16k byte pages.The content of the PPAGE register
is used to map the logical middle page ranging from address $8000 to $BFFF to any physical 16K bytes
page in the physical memory
1
. Shown within the blocks are a protection/options field and user defined
Flash protected sectors.
The FPOPEN bit in the FPROT register (see
3.3.5
) can globally protect the entirety of the memory block.
However, two protected areas, one starting from the Flash page starting address (called lower) towards
higheraddressesandtheotheronegrowingdownwardfromtheFlashpageendaddress(calledhigher)can
be activated. The latter is mainly targeted to hold the boot loader code since it covers the vector space. All
the other areas may be used to keep critical parameters.
The pagination process using the PPAGE register is handled the Star12 CPU.
The Flash module register space covers the addresses BASE + $100 to BASE + $10F.
NOTES
:
1. By placing $3F or $3E in the PPAGE register, the bottom respectively top “fixed” 16Kbytes pages can be seen twice in the
MCU memory map.
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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