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參數(shù)資料
| 型號： | FS6370-01G-XTD |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 3-PLL EEPROM 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1115 (CN2011-ZH PDF) |
| 其它名稱： | 766-1025 |
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FS6370
If a stop bit is transmitted before the entire write command sequence is complete, then the command is aborted and no data is written
to memory. If more than eight bits are transmitted before the stop bit is sent, then the EEPROM will clear the previously loaded data
byte and will begin loading the data buffer again.
6.1.2. Acknowledge Polling
The EEPROM does not acknowledge while it internally commits data to memory. This feature can be used to increase data throughput
by determining when the internal write cycle is complete.
The process is to initiate the random register write procedure with a START condition, the EEPROM device address, and the write
command bit (R/W=0).
If the EEPROM has completed its internal 4 ms write cycle, the EEPROM will acknowledge on the next clock, and the write command
can continue.
If the EEPROM has not completed the internal 4 ms write cycle, the random register write procedure must be restarted by sending the
START condition, device address and R/W bit. This sequence must be repeated until the EEPROM acknowledges.
6.1.3. Read Operation
The EEPROM supports both the random register read procedure and the sequential register read procedure (both are outlined in
Section 6).
For sequential read operations, the EEPROM has an internal address pointer that increments by one at the end of each read operation.
The pointer directs the EEPROM to transmit the next sequentially addressed data byte, allowing the entire memory contents to be read
in one operation.
6.2 Direct Register Programming
The FS6370 control registers may be directly accessed by simply using the FS6370 device address in the read or write operations. The
operation of the device will follow the register values. The register map of the FS6370 is identical to that of the EEPROM shown in
The FS6370 supports the random read and write procedures, as well as the sequential read and write procedures described in Section
8.
The device address for the FS6370 is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
0
7.0 Cost Reduction Migration Path
The FS6370 is compatible with the programmable register-based FS6377 or a fixed-frequency ROM-based clock generator. Attention
should be paid to the board layout if a migration path to either of these devices is desired.
7.1 Programming Migration Path
If the design can support I2C programming overhead, a cost reduction from the EEPROM-based FS6370 to the register-based FS6377
is possible.
Figure 5 shows the five pins that may not be compatible between the various devices if programming of the FS6370 or the FS6377 is
desired.
Rev. 3 | Page 7 of 28 | www.onsemi.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6370-01G-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 EE PROG 3-PLL CLOCK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6377 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01 | 制造商:AMI 制造商全稱:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G | 制造商:AMI 制造商全稱:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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