參數(shù)資料
型號(hào)： FPD85308
廠商： National Semiconductor Corporation
英文描述： Panel Timing Controller
中文描述： 小組定時(shí)控制器
文件頁(yè)數(shù)： 9/31頁(yè)
文件大?。?/td> 474K
代理商： FPD85308
Functional Description
FPD-LINK Receiver
The LVDS based FPD-Link Receiver receives inputs video
data and control timing. Four LVDS channels plus clock
provide 24-bit color. Three LVDS channels can be used for
18-bit color.
The video data is regenerated to a parallel data stream and
routed to the 8 to 6 Bit Translator. The General Purpose
Outputs (GPOs) continue outputting the programmed control
sequence at a reduced frame rate. RSTZ initialized the chip
with the default register values. EEPROM configuration data
is loaded if EEPROM is detected. (EEPROM address 80H =
“00”).
Spread Spectrum Support
The FPD-Link receiver supports graphics controllers with
Spread Spectrum interfaces for reducing EMI. The Spread
Spectrum method supported is Center Spread. A maximum
of 2% Center Spread at a modulation frequency of 200 KHz
is supported.
8 to 6 Bit Translator
8-bit data is reduced to a 6-bit data path via a time multi-
plexed dithering technique or a simple truncation of the
LSBs. This function is enabled via the Input Control Register
bits 4 and 3. See Table 2 Input Format Control register.
Data Alignment
This function delays and aligns data to match the CD/panel
architecture. Programmable selections in the Output Format
Control Register bits 0 and 1 provide support for various
LCD panel architectures. See Figures 12, 13, 14, 15, 16 for
additional explanation.
Dual Bus, Single Port CD Interface
When interfacing two busses to a bank of single port column
drivers, the RGB data must be aligned/delayed with respect
to the size of the column drivers being used. The CD Size
register is programmed to support single port column drivers
of up to 384 outputs (128 pixels).
Dual Bus, Dual Port CD Interface
When interfacing with dual port column drivers, data is sim-
ply output with odd and even data on separate outputs.
Single Bus, Single Port CD Interface
The single bus, single port column driver interface provides
support of existing SVGA systems. All data is output on a
single bus. The second bus can be turned off when using
this configuration.
Output Formatting
The output formatting function provides several capabilities
to reduce noise EMI and to generate customized timing.
These capabilities are selectable/programmable via the Out-
put Format Control, Output Enable/Polarity Control, and Out-
put Drive Control Registers. See Table 2 for specific bit
definitions.
Data Bus Skewing
This function aligns the two output channels in either a
non-skewed data format (simultaneous switching) or a
skewed data format. The skewed format delays the even
channel data and control by
1
2
clock. This reduces the
number of outputs which switch simultaneously. See Figures
12, 13, 14, 15, 16 Data Bus Skewing is enabled by setting
bit 2 in the Output Format Control register.
Programmable Slew Rates
Programmable edge rates allow the Data, Polarity, Start
Pulse, and Clock outputs to be adjusted for better imped-
ance matching for noise and EMI reduction. Bits [7:6] of the
Output Enable/Polarity Control Register control OSP and
ESP outputs. The Output Drive Control register control the
OCLK, ECLK, ORGB/OPOL, ERGB/EPOL outputs.
Polarity Generation
When enabled, a polarity indication (OPOL, EPOL) is output
for each data bus. When in the dual bus output configuration,
if the number of transitions from pixel to pixel exceed 18 bits
from a total of 36 bits, the data is then inverted and a polarity
indication corresponding to that bus is set active. In the
single bus (ORGB bus) applications such as SVGA, when
the number of pixel to pixel transitions exceed 9 bits from a
total of 18 bits, the data is inverted and the OPOL is set
active. This features requires the use of a CD with a polarity
input. In SKEWED dual output data bus applications, OPOL
and EPOL are aligned with their respective buses and
should be used as the Polarity generation input to the CD
which supports dual bus/Polarity generation. In Non-Skewed
dual output bus applications, OPOL is aligned with both data
buses and should be used as the Polarity Generation input
to the CD. The polarity function is enabled by setting bit 6 of
the Output Format Control register (EEPROM address D2).
The OCLK and ECLK polarity is also programmable. Inver-
sion and TRI-STATE control of OCLK and ECLK is provided
by bits [3:0] of the Output Enable/Polarity Control Register.
The ERGB/ESP/EPOL and ORGB/OSP/OPAL outputs can
be disabled (TRI-STATE) using bits [5:4] of the Output
Enable/Polarity Control register.
Programmable Positioning of CD Start Pulse
The position of the CD Start Pulse is programmable. This
allows use with column drivers having non-standard start
pulse timing. The CD Start Pulse position is determined by
bits [3:0] of the Output Format Control Register (EEPROM
address D3).
Data Blanking
Data, Polarity, Start Pulse and Clock can be blanked (forced
to “0”) during horizontal and/or vertical blanking periods.
GPO [8] is programmed to correspond to display periods.
When GPO [8] is low, outputs are forced to “0”. This reduces
amount of switching over the frame time thus reducing
power. See GPO programming procedure in APPENDIX A:
GPO Programming Examples
Line Inversion
When enabled (Bit 3 of the Output Format Register), the
polarity of the output data is determined by GPO [0]. Bit 4
defines the relationship between GPO [0] and the output
data. Bit 5 provides a variation of this where the Odd and
Even data is of different polarity. This could be used in a
system with CDs on both top and bottom of the panel in
which dot inversion is desired.
F
www.national.com
9
相關(guān)PDF資料
PDF描述
FPD85310VJD Panel Timing Controller
FPD85310 Panel Timing Controller
FPD87208AXAVS +2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS⑩ Outputs
FPD87208 +2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS⑩ Outputs
FPD87310 Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FPD85310 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Panel Timing Controller
FPD85310VJD 功能描述:IC CTRLR PANEL TIMING 100-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
FPD87208 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS⑩ Outputs
FPD87208AXAVS 制造商:Rochester Electronics LLC 功能描述:2.5V XGA/WXGA TIMING CONTROLER - Bulk
FPD87310 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*