FM8P51
Rev1.2 Mar 15, 2005
P.31/FM8P51
FEELING
TECHNOLOGY
Besides, both of these bits are cleared by software. The RCBF flag also will be set to “1”, cleared by software or
by reading out SPIRCB register.
9. Read out the SPIRCB register before next byte transmission being finished if needed.
2.7.2.2 Slave Mode without SSE Control (SSEMOD = 1)
In this slave mode, the data is transmitted and received as the external clock pulses appear on SCK pin. Once the
clock pulse appear on SCK pin, data in SPITXB will be loaded into SPISR and start to shift in/out, then transmit
buffer empty detect bit (TXBF), and interrupt flag bits (SPITXIF, TXBFIF) are set. And then user could write the next
byte data to SPITXB register before the 8-bit data transmission is completed if needed. Once the 8-bits of data have
been received, the data in SPISR will be moved to the SPIRCB register, then buffer full detect bit (RCBF), interrupt
flag bits (SPIRCIF, RCBFIF) are set. And then user could read out the SPIRCB register before next 8-bit data
transmission is completed if needed.
The SSB pin allows a synchronous slave mode. The SPI must be in slave mode with SSB pin control enabled
(SPICON<2:0> = 101). When the SSB pin is low, transmission and reception are enabled and the SDO pin is driven.
When the SSB pin goes high, the SDO pin is no longer driven, even if in the middle of transmitted byte, and
becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application.
When the SPI module resets, the bit counter is forced to 0. This can be done by forcing the SSB pin to high level or
clearing the SPION bit (SPICON<6>).
How to transmit/receive data in this slave mode:
1. Enable SPI function by setting the SPION (SPICON<6>) bit.
2. Enable/disable the SSB pin control by programming SPIM2:SPIM0 (SPICON<2:0>) bits.
3. Write the data that you want to transmit to SPITXB register if needed.
4. Wait the external clock pulses appear on SCK pin to start transmit.
5. When the 8-bit data transmission starts, both of the SPITXIF and TXBFIF interrupt flags will set to 1. Besides,
both of these bits are cleared by software. The TXBF flag also will be set to “1”, cleared by software or by
writting data to SPITXB register.
6. Write next new data to SPITXB register before this byte transmission being finished if needed.
7. When the 8-bit data transmission is completed, both of the SPIRCIF and RCBFIF interrupt flags will set to 1.
Besides, both of these bits are cleared by software. The RCBF flag also will be set to “1”, cleared by software or
by reading out SPIRCB register.
8. Read out the SPIRCB register before next byte transmission being finished if needed.