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參數(shù)資料
| 型號(hào)： | FIN24CGFX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | uSerDes Low Voltage 24-Bit Bi-Directional Serializer/Deserializer |
| 中文描述： | LINE TRANSCEIVER, PBGA42 |
| 封裝： | 3.5 MM, LEAD FREE, MO-195, BGA-42 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 758K |
| 代理商： | FIN24CGFX |
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www.fairchildsemi.com
F
PLL Circuitry
The CKREF input signal is used to provide a reference to the
PLL. The PLL will generate internal timing signals capable of
transferring data at 26 times the incoming CKREF signal. The
output of the PLL is a Bit Clock that is sent with the serial data
stream.
There are two ways to disable the PLL. The PLL can be dis-
abled by entering the Mode 0 state (S1 = S2 = 0). The PLL will
disable immediately upon detecting a LOW on both the S1 and
S2 signals. Any of the other modes are entered by asserting
either S1 or S2 HIGH and by providing a CKREF signal the PLL
will power-up and go through a lock sequence. One must wait
the specified number of clock cycles prior to capturing valid data
into the parallel port. When the SerDes chipset transitions from
a power down state (S1, S2 = 0, 0) to a powered state (example
S1, S2 = 1, 1), CKP on the deserializer will transition LOW for a
short duration, and will return HIGH. Following this, the signal
level of the deserializer at CKP will correspond to the serializer
signal levels.
An alternate way of powering down the PLL is by stopping the
CKREF signal either HIGH or LOW. Internal circuitry detects the
lack of transitions and shuts the PLL and serial I/O down. Inter-
nal references will not however be disabled allowing for the PLL
to power-up and re-lock in a lesser number of clock cycles than
when exiting Mode 0. When a transition is seen on the CKREF
signal the PLL will once again be reactivated.
Application Mode Diagrams
MODE equals 3: Unidirectional Data Transfer
FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer
Figure 8 shows the basic operation diagram when a pair of Ser-
Des is configured in an unidirectional operation mode.
Master Operation:
The device will... (Please refer to Figure 8)
1. Be configured as a serializer at power-up based on the value
of the DIRI signal.
2. Accept CKREF_M word clock and generate a bit clock with
embedded word boundary. This bit clock will be sent to the
slave device through the CKSO port.
3. Receive parallel data on the rising edge of STROBE_M.
4. Generate and transmit serialized data on the DS signals
which is source synchronous with CKSO.
5. Generate an embedded word clock for each strobe signal.
Slave Operation:
The device will...
1. Be configured as a deserializer at power-up based on the
value of the DIRI signal.
2. Accept an embedded word boundary bit clock on CKSI.
3. Deserialize the DS Data stream using the CKSI input clock.
4. Write parallel data onto the DP_S port and generate the
CKP_S. CKP_S will only be generated when a valid data
word occurs.
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