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參數(shù)資料
| 型號： | FIN24CGFX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | uSerDes Low Voltage 24-Bit Bi-Directional Serializer/Deserializer |
| 中文描述： | LINE TRANSCEIVER, PBGA42 |
| 封裝： | 3.5 MM, LEAD FREE, MO-195, BGA-42 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 758K |
| 代理商： | FIN24CGFX |
www.fairchildsemi.com
8
F
Embedded Word Clock Operation
The FIN24C sends and receives serial data source synchro-
nously with a bit clock. The bit clock has been modified to create
a word boundary at the end of each data word. The word
boundary has been implemented by skipping a LOW clock
pulse. This appears in the serial clock stream as three consecu-
tive bit times where signal CKSO remains HIGH.
In order to implement this sort of scheme two extra data bits are
required. During the word boundary phase the data will toggle
either HIGH-then-LOW or LOW-then-HIGH dependent upon the
last bit of the actual data word. Table 2 provides some examples
showing the actual data word and the data word with the word
boundary bits added. Note that a 24-bit word will be extended to
26 bits during serial transmission. Bit 25 and Bit 26 are defined
with-respect-to Bit 24. Bit 25 will always be the inverse of Bit 24
and Bit 26 will always be the same as Bit 24. This insures that a
“0”
“1” and a “1”
“0” transition will always occur during the
embedded word phase where CKSO is HIGH.
The serializer generates the word boundary data bits and the
boundary clock condition and embeds them into the serial data
stream. The deserializer looks for the end of the word boundary
condition to capture and transfer the data to the parallel port.
The deserializer only uses the embedded word boundary infor-
mation to find and capture the data. These boundary bits are
then stripped prior to the word being sent out of the parallel port.
TABLE 2. Word Boundary Data Bits
LVCMOS Data I/O
(Figure 6)
The LVCMOS input buffers have a nominal threshold value
equal to of V
DDP
. The input buffers are only operational when
the device is operating as a serializer. When the device is oper-
ating as a deserializer the inputs are gated off to conserve
power.
The LVCMOS 3-STATE output buffers are rated for a source/
sink current of 2mAs at 1.8V. The outputs are active when the
DIRI signal is asserted LOW. When the DIRI signal is asserted
HIGH the bi-directional LVCMOS I/Os will be in a HIGH-Z state.
Under purely capacitive load conditions the output will swing
between GND and V
DDP
.
Unused LVCMOS input buffers must be tied off to either a valid
logic LOW or a valid logic HIGH level to prevent static current
draw due to a floating input. Unused LVCMOS outputs should
be left floating. Unused bidirectional pins should be connected
to GND through a high value resistor. If a FIN24C devices is
configured as an unidirectional serializer then unused data I/O
can be treated as unused inputs. If the FIN24C is hardwired as
a deserializer then unused date I/O can be treated as unused
outputs.
FIGURE 6. LVCMOS I/O
Differential I/O Circuitry
(Figure 7)
The FIN24C employs FSC proprietary CTL I/O technology. CTL
is a low power, low EMI differential swing I/O technology. The
CTL output driver generates a constant output source and sink
current. The CTL input receiver senses the current difference
and direction from the corresponding output buffer to which it is
connected. This differs from LVDS which uses a constant cur-
rent source output but a voltage sense receiver. Like LVDS an
input source termination resistor is required to properly termi-
nate the transmission line. The FIN24C device incorporates an
internal termination resistor on the CKSI receiver and a gated
internal termination resistor on the DS input receiver. The gated
termination resistor insures proper termination regardless of
direction of data flow. The relative greater sensitivity of the cur-
rent sense receiver of CTL allows it to work at much lower cur-
rent drive and correspondingly a much lower voltage.
During power-down mode the differential inputs will be disabled
and powered down and the differential outputs will be placed in
a HIGH-Z state. CTL inputs have an inherent failsafe capability
that supports floating inputs. When the CKSI input pair of the
serializer is unused it can reliably be left floating. Alternately
both of the inputs can be connected to ground. CTL inputs
should never be connected to V
DD
. When the CKSO output of
the deserializer is unused it should be allowed to float.
FIGURE 7. Bi-Directional Differential I/O Circuitry
24-Bit Data Words
24-Bit Data Word with Word Boundary
Hex
Hex
Binary
Binary
FFFFFFh
1111 1111 1111 1111 1111 1111b
2FFFFFFh 10 1111 1111 1111 1111 1111 1111b
555555h
0101 0101 0101 0101 01010 0101b 1555555h 01 0101 0101 0101 0101 0101 0101b
xxxxxxh
0xxx xxxx xxxx xxxx xxxx xxxxb
1xxxxxxh
01 0xxx xxxx xxxx xxxx xxxx xxxxb
xxxxxxh
1xxx xxxx xxxx xxxx xxxx xxxxb
2xxxxxxh
10 1xxx xxxx xxxx xxxx xxxx xxxxb
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