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參數資料
| 型號： | FIN24CGFX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | uSerDes Low Voltage 24-Bit Bi-Directional Serializer/Deserializer |
| 中文描述： | LINE TRANSCEIVER, PBGA42 |
| 封裝： | 3.5 MM, LEAD FREE, MO-195, BGA-42 |
| 文件頁數： | 13/22頁 |
| 文件大?。?/td> | 758K |
| 代理商： | FIN24CGFX |
13
www.fairchildsemi.com
F
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Note 5:
Typical Values are given for V
DD
= 2.775V and T
A
= 25 C. Positive current values refer to the current flowing into device and negative values means current flowing out
of pins. Voltage are referenced to GROUND unless otherwise specified (except V
OD
and V
OD
).
Note 6:
Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO). Signals are edge aligned. Both outputs should have iden-
tical load conditions for this test to be valid.
Note 7:
The power-downtime is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The specific number of
clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device.
Note 8:
Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high state. Skew should only be
measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew from the serializer, load variations and ISI
and jitter effects.
Note 9:
Rising edge of CKP will appear approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP will occur approximately 8 bit times after a data
transition or 6 bit times after the first falling edge of CSKO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP
path and propagation delay differences on the various data pins. Note that if the CKREF is not equal to STROBE for the serializer then the CKP signal will not maintain a 50% duty
cycle. The low time of the CKP will remain 13 bit times.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 5)
Serializer Input Operating Conditions
t
TCP
CKREF Clock Period
(10 MHz - 20 MHz)
See Figure 17
50.0
T
100
ns
f
REF
CKREF Frequency Relative
CKREF
1.1 *
f
ST
20.0
MHz
to Strobe Frequency
does not equal STROBE
t
CPWH
CKREF Clock High Time
0.2
0.5
T
t
CPWL
CKREF Clock Low Time
0.2
0.5
T
t
CLKT
LVCMOS Input Transition Time
See Figure 17
90.0
ns
t
SPWH
STROBE Pulse Width HIGH/LOW
See Figure 17
(T x 4)/26
(T x 22)/26
ns
f
MAX
Maximum Serial Data Rate
CKREF x 26
260
520
Mb/s
t
STC
DP
(n)
Setup to STROBE
DIRI = 1
2.5
ns
t
HTC
DP
(n)
Hold to STROBE
see Figure 6 (f = 5MHz)
2.0
ns
f
REF
CKREF Frequency Relative to Strobe Frequency CKREF Does Not Equal STROBE
1.1 x f
STROBE
20.0
MHz
Serializer AC Electrical Characteristics
t
TCCD
Transmitter Clock Input to
See Figure 20, DIRI = 1,
33a 1.5
35a 6.5
ns
Clock Output Delay
CKREF = STROBE
t
SPOS
CKSO Position Relative to DS
See Figure 23, (Note 6)
50.0
250
ps
PLL AC Electrical Characteristics
t
TPLLS0
Serializer Phase Lock Loop Stabilization Time
See Figure 19
200
s
t
TPLLD0
PLL Disable Time Loss of Clock
See Figure 24
30.0
s
t
TPLLD1
PLL Power-Down Time
See Figure 25, (Note 7)
20.0
ns
Deserializer Input Operation Conditions
t
S_DS
Serial Port Setup Time, DS-to-CKSI
see Figure 22, (Note 8)
1.4
ns
t
H_DS
Serial Port Hold Time, DS-to-CKS
see Figure 22, (Note 8)
250
ps
Deserializer AC Electrical Characteristics
t
RCOP
Deserializer Clock Output (CKP OUT) Period
see Figure 18
50.0
T
500
ns
t
RCOL
CKP OUT Low Time
see Figure 18 (Rising Edge Strobe)
Serializer Source STROBE = CKREF
Where a = (1/f)/26 (Note 9)
13a-3
13a 3
ns
t
RCOH
CKP OUT High Time
13a-3
13a 3
ns
t
PDV
Data Valid to CKP LOW
see Figure 18 (Rising Edge Strobe)
8a-6
8a 1
ns
Where a = (1/f)/26 (Note 9)
t
ROLH
Output Rise Time (20% to 80%)
C
L
= 5 pF
2.5
ns
t
ROHL
Output Fall time (80% to 20%)
see Figure 15
2.5
ns
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