參數(shù)資料
型號: FDS6912
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: JFETs
英文描述: Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
中文描述: 6 A, 30 V, 0.028 ohm, 2 CHANNEL, N-CHANNEL, Si, POWER, MOSFET
封裝: SOIC-8
文件頁數(shù): 2/8頁
文件大小: 219K
代理商: FDS6912
FDS6912 Rev E (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
BV
DSS
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250
μ
A
I
D
= 250
μ
A, Referenced to 25
°
C
30
V
Breakdown Voltage Temperature
20
mV/
°
C
V
DS
= 24 V,
V
GS
= 20 V,
V
GS
= –20 V
V
GS
= 0 V
T
J
= 55
°
C
V
DS
= 0 V
V
DS
= 0 V
1
10
100
–100
μ
A
I
GSSF
I
GSSR
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
nA
nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
, I
D
= 250
μ
A
I
D
= 250
μ
A, Referenced to 25
°
C
1
2
–5
3
V
Gate Threshold Voltage
mV/
°
C
V
GS
= 10 V,
V
GS
= 4.5 V,
V
GS
= 10 V,
V
DS
= 10 V,
I
D
= 6 A
T
J
= 125
°
C
I
D
= 4.9 A
V
DS
= 5 V
I
D
= 6 A
0.024
0.034
0.035
0.028
0.048
0.042
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
20
A
S
20
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
740
170
75
pF
pF
pF
V
DS
= 15 V,
f = 1.0 MHz
V
GS
= 0 V,
Switching Characteristics
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
(Note 2)
8
13
18
8
7
3.8
2.5
16
24
29
16
10
ns
ns
ns
ns
nC
nC
nC
V
DD
= 15 V,
V
GS
= 10 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 10 V,
V
GS
= 5 V
I
D
= 6 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
1.3
1.2
A
V
V
GS
= 0 V,
I
S
= 1.3 A
(Note 2)
0.75
Notes:
1.
R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) 78°/W when
mounted on a 0.5in
2
pad of 2 oz copper
b) 125°/W when
mounted on a 0.02
in
pad of 2 oz
copper
c) 135°/W when mounted on a
minimum mounting pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
F
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參數(shù)描述
FDS6912_0007 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
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FDS6912A_Q 功能描述:MOSFET Dual N-Channel 30V RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS(導(dǎo)通):0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube