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參數(shù)資料
| 型號： | FDS6812 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET |
| 中文描述： | 雙N溝道邏輯電平PWM優(yōu)化的PowerTrench MOSFET的 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 79K |
| 代理商： | FDS6812 |
FDS6812A Rev B (W)
Electrical Characteristics
Symbol
T
A
= 25°C unless otherwise noted
Test Conditions
Parameter
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
BV
DSS
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
V
GS
= 0 V,
I
D
= 250
μ
A, Referenced to 25
°
C
I
D
= 250
μ
A
20
V
Breakdown Voltage Temperature
14
mV/
°
C
V
DS
= 16 V,
V
DS
= 16 V, V
GS
= 0 V, T
J
= 55
°
C
V
GS
= 12 V,
V
DS
= 0 V
V
GS
= –12 V, V
DS
= 0 V
V
GS
= 0 V
1
10
100
–100
μ
A
I
GSSF
I
GSSR
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
nA
nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
,
I
D
= 250
μ
A, Referenced to 25
°
C
I
D
= 250
μ
A
0.6
0.8
–3.2
1.5
V
Gate Threshold Voltage
mV/
°
C
V
GS
= 4.5 V,
V
GS
= 2.5 V,
V
GS
= 4.5 V,I
D
= 7.5 A,T
J
= 125
°
C
V
GS
= 4.5V,
V
DS
= 5 V
V
DS
= 5 V,
I
D
= 6.7 A
I
D
= 6.7 A
I
D
= 5.3 A
17
22
23
22
35
29
m
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
15
A
S
37
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
1082
277
130
pF
pF
pF
V
DS
= 10 V,
f = 1.0 MHz
V
GS
= 0 V,
Switching Characteristics
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
(Note 2)
8
8
24
8
12
2
3
16
16
38
16
19
ns
ns
ns
ns
nC
nC
nC
V
DD
= 10 V,
V
GS
= 4.5 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 10 V,
V
GS
= 4.5 V
I
D
=6.7 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
1.3
1.2
A
V
V
GS
= 0 V,
I
S
= 1.3 A
(Note 2)
0.7
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) 78°C/W when
mounted on a 0.5in
2
pad of 2 oz copper
b) 125°C/W when
mounted on a 0.02
in
pad of 2 oz
copper
c) 135°C/W when mounted on a
minimum mounting pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
F
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