參數(shù)資料
型號(hào): FDMS9620S
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: JFETs
英文描述: Dual N-Channel PowerTrench㈢ MOSFET Q1: 30V, 16A, 21.5mヘ Q2: 30V, 18A, 13mヘ
中文描述: 7.5 A, 30 V, 0.0215 ohm, 2 CHANNEL, N-CHANNEL, Si, POWER, MOSFET
封裝: ROHS COMPLIANT, POWER 56, 8 PIN
文件頁數(shù): 5/9頁
文件大小: 286K
代理商: FDMS9620S
F
M
2007 Fairchild Semiconductor Corporation
FDMS9620S Rev.D
www.fairchildsemi.com
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs Drain
to Source Voltage
Figure 9. Forward Bias Safe
Operating Area
Figure 10. Single Pulse Maximum
Power Dissipation
Figure 11. Transient Thermal Response Curve
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
0
2
4
6
8
10
12
0
2
4
6
8
10
I
D
= 7.5A
V
DD
= 20V
V
DD
= 15V
V
DD
=10V
Q
g
,
GATE CHARGE(nC)
V
G
,
G
0.1
1
10
100
1000
30
f = 1MHz
V
GS
= 0V
C
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
rss
C
oss
C
iss
30
0.1
1
10
100
0.01
0.1
1
10
100
DC
10s
1s
100ms
10ms
1ms
SINGLE PULSE
T
J
= MAX RATE
R
θ
JA
= 120
o
C
T
A
= 25
o
C
THIS AREA IS LIMITED
BY r
DS(ON)
V
DS
, DRAIN to SOURCE VOLTAGE (V)
I
D
,
D
10
-3
10
-2
10
t, PULSE WIDTH (s)
-1
10
0
10
1
10
2
10
3
1
10
100
0.5
V
GS
= 10V
SINGLE PULSE
R
θ
JA
= 120
o
C/W
T
A
= 25
o
C
P
(
P
)
,
P
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
0.01
0.1
1
DUTY CYCLE-DESCENDING ORDER
N
I
θ
J
t, RECTANGULAR PULSE DURATION (s)
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
R
θ
JA
= 120
o
C/W
2
P
DM
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JA
x R
θ
JA
+ T
A
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