參數(shù)資料
型號(hào)： FDC37C67X
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 外設(shè)及接口
英文描述： ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： QFP-100
文件頁(yè)數(shù)： 185/194頁(yè)
文件大?。?/td> 546K
代理商： FDC37C67X
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185
ECP PARALLEL PORT TIMING
Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the
peak 500KBytes/sec allowed in the forward
direction using DMA. The state machine does
not examine nACK and begins the next transfer
based on Busy. Refer to Figure 18.
ECP Parallel Port Timing
The timing is designed to allow operation at
approximately 2.0 Mbytes/sec over a 15ft cable.
If a shorter cable is used then the bandwidth
will increase.
Forward-Idle
When the host has no data to send it keeps
HostClk (nStrobe) high and the peripheral will
leave PeriphClk (Busy) low.
Forward Data Transfer Phase
The interface transfers data and commands
from the host to the peripheral using an inter-
locked PeriphAck and HostClk. The peripheral
may indicate its desire to send data to the host
by asserting nPeriphRequest.
The Forward Data Transfer Phase may be
entered from the Forward-Idle Phase. While in
the
Forward
Phase
asynchronously assert the nPeriphRequest
(nFault) to request that the channel be reversed.
When the peripheral is not busy it sets
PeriphAck (Busy) low. The host then sets
HostClk (nStrobe) low when it is prepared to
send data. The data must be stable for the
specified setup time prior to the falling edge of
HostClk.
The
peripheral
the
peripheral
may
then
sets
PeriphAck (Busy) high to acknowledge the
handshake. The host then sets HostClk
(nStrobe) high. The peripheral then accepts
the data and sets PeriphAck (Busy) low,
completing the transfer. This sequence is shown
in Figure 18.
The timing is designed to provide 3 cable
round-trip times for data setup if Data is driven
simultaneously with HostClk (nStrobe).
Reverse-Idle Phase
The peripheral has no data to send and keeps
PeriphClk high. The host is idle and keeps
HostAck low.
Reverse Data Transfer Phase
The interface transfers data and commands
from the peripheral to the host using an inter-
locked HostAck and PeriphClk.
The Reverse Data Transfer Phase may be en-
tered from the Reverse-Idle Phase. After the
previous byte has beed accepted the host sets
HostAck (nALF) low. The peripheral then sets
PeriphClk (nACK) low when it has data to send.
The data must be stable for the specified setup
time prior to the falling edge of PeriphClk. When
the host is ready to accept a byte it sets
HostAck (nALF) high to acknowledge the
handshake. The peripheral then sets PeriphClk
(nACK) high. After the host has accepted the
data it sets HostAck (nALF) low, completing the
transfer.
This sequence is shown in Figure 19.
相關(guān)PDF資料
PDF描述
FDC37C957FR ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS
FDC37M600 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
FDC37M601 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
FDC37M602 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
FDC37M603 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
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