
131
SYSTEM MANAGEMENT INTERRUPT (SMI)
The FDC37C67x implements a group nSMI
output pin. The System Management Interrupt
is a non-maskable interrupt with the highest
priority level used for transparent power
management. The nSMI group interrupt output
consists of the enabled interrupts from each of
the functional blocks in the chip. The interrupts
are enabled onto the group nSMI output via the
SMI Enable Registers 1 and 2. The nSMI output
is then enabled onto the group nSMI output pin
via bit[7] in the SMI Enable Register 2.
The logic equation for the nSMI output is as
follows:
nSMI
=
(EN_PINT
(EN_U2INT
and
(EN_U1INT
and
(EN_FINT
and
(EN_WDT
and
(EN_MINT
and
(EN_KINT
and
(EN_IRINT and IRQ_IRINT)
and
IRQ_PINT)
IRQ_U2INT)
IRQ_U1INT)
IRQ_FINT)
IRQ_WDT)
IRQ_MINT)
IRQ_KINT)
or
or
or
or
or
or
or
REGISTERS
The following registers can be accessed when in
configuration mode at Logical Device 8,
Registers B4-B7 and when not in configuration
they can be accessed through the Index and
Data Register (refer to Table 47B).
SMI Enable Registers
SMI Enable Register 1
(Configuration Register B4, Logical Device 8)
This register is used to enable the different
interrupt sources onto the group nSMI output.
SMI Enable Register 2
(Configuration Register B5, Logical Device 8)
This register is used to enable additional
interrupt sources onto the group nSMI output.
This register is also used to enable the group
nSMI output onto the nSMI Serial/Parallel IRQ
pin and the routing of 8042 P12 internally to
nSMI.
SMI Status Registers
SMI Status Register 1
(Configuration Register B6, Logical Device 8)
This register is used to read the status of the
SMI input events. Note: The status bit gets set
whether or not the interrupt is enabled onto the
group SMI output.
SMI Status Register 2
(Configuration Register B7, Logical Device 8)