參數(shù)資料
型號: EVAL-ADV7180-32EBZ
廠商: Analog Devices Inc
文件頁數(shù): 24/116頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADV7180
標(biāo)準(zhǔn)包裝: 1
系列: Advantiv®
主要目的: 視頻,SDTV 視頻解碼器 - NTSC,PAL,SECAM
嵌入式:
已用 IC / 零件: ADV7180
主要屬性: CVBS(復(fù)合),Y/C(S 視頻)和 YPrPb(元件)輸入
次要屬性: 8 位 ITU-R BT.656 YCrCb 4:2:2 輸出
已供物品:
Data Sheet
ADV7180
Rev. I | Page 15 of 116
64-LEAD LQFP
64
VS
63
FIE
LD
62
P
12
61
P
13
60
P
14
59
P
15
58
DV
DD
57
DG
ND
56
GP
O2
55
GP
O3
54
S
CL
K
53
SD
AT
A
52
AL
S
B
51
R
ESET
50
NC
49
A
IN
6
47
AIN4
46
AIN3
45
NC
42
NC
43
AGND
44
NC
48
AIN5
41
NC
40
AVDD
39
VREFN
37
AGND
36
AIN2
35
AIN1
34
TEST_0
33
NC
38
VREFP
2
HS
3
DGND
4
DVDDIO
7
P9
6
P10
5
P11
1
INTRQ
8
P8
9
SFL
10
DGND
12
GPO1
13
GPO0
14
P7
15
P6
16
P5
11
DVDDIO
17
P4
18
P3
19
P2
20
LLC
21
X
T
AL
1
22
X
T
A
L
23
DV
DD
24
DG
ND
25
P1
26
P0
27
NC
28
NC
29
P
W
RDW
N
30
EL
PF
31
PVD
D
32
AG
ND
PIN 1
ADV7180
LQFP
TOP VIEW
(Not to Scale)
NC = NO CONNECT
05700-
008
Figure 10. 64-Lead LQFP Pin Configuration
Table 11. 64-Lead LQFP Pin Function Description
Pin No.
Mnemonic
Type
Description
1
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
2
HS
O
Horizontal Synchronization Output Signal.
3, 10, 24, 57
DGND
G
Digital Ground.
4, 11
DVDDIO
P
Digital I/O Supply Voltage (1.8 V to 3.3 V).
5 to 8, 14 to 19,
25, 26, 59 to 62
P11 to P8,
P7 to P2, P1,
P0, P15 to P12
O
Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.
9
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.
12, 13, 55, 56
GPO0 to GPO3
O
General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices.
20
LLC
O
This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz but varies up or down according to video line length.
21
XTAL1
O
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode,
the crystal must be a fundamental crystal.
22
XTAL
I
This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external
1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental
crystal.
23, 58
DVDD
P
Digital Supply Voltage (1.8 V).
27, 28, 33, 41, 42,
44, 45, 50
NC
No Connect. These pins are not connected internally.
29
PWRDWN
I
A logic low on this pin places the ADV7180 in power-down mode.
30
ELPF
I
The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 58.
31
PVDD
P
PLL Supply Voltage (1.8 V).
32, 37, 43
AGND
G
Analog Ground.
34
TEST_0
I
This pin must be tied to DGND.
35, 36, 46 to 49
AIN1 to AIN6
I
Analog Video Input Channels.
38
VREFP
O
Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.
39
VREFN
O
Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.
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