參數(shù)資料
型號： EVAL-ADV7180-32EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 22/116頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADV7180
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，SDTV 視頻解碼器 - NTSC，PAL，SECAM
嵌入式： 否
已用 IC / 零件： ADV7180
主要屬性： CVBS（復(fù)合），Y/C（S 視頻）和 YPrPb（元件）輸入
次要屬性： 8 位 ITU-R BT.656 YCrCb 4:2:2 輸出
已供物品： 板
Data Sheet
ADV7180
Rev. I | Page 13 of 116
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
32-LEAD LFCSP
05
70
0-
0
57
NOTES
1. THE EXPOSEDPAD MUST BE CONNECTEDTO GND.
1
2
3
4
5
6
7
8
HS
DGND
DVDDIO
SFL
P7
P6
P5
P4
17
18
19
20
21
22
23
24
ELPF
PVDD
AIN1
VREFP
VREFN
AVDD
AIN2
AIN3
PIN1
INDICATOR
ADV7180
LFCSP
TOP VIEW
(Not to Scale)
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
P0
P1
DV
DD
XT
A
L
XT
A
L
1
LL
C
P2
P3
R
ESE
T
AL
S
B
S
DAT
A
SC
L
K
DG
ND
DV
DD
VS/
F
IE
L
D
IN
TR
Q
Figure 8. 32-Lead LFCSP Pin Configuration
Table 9. 32-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1
HS
O
Horizontal Synchronization Output Signal.
2, 29
DGND
G
Ground for Digital Supply.
3
DVDDIO
P
Digital I/O Supply Voltage (1.8 V to 3.3 V).
4
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
5 to 10, 15, 16
P7 to P2, P1, P0
O
Video Pixel Output Port.
11
LLC
O
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or
down according to video line length.
12
XTAL1
O
This pin should be connected to the 28.6363 MHz crystal or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
13
XTAL
I
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
14, 30
DVDD
P
Digital Supply Voltage (1.8 V).
17
ELPF
I
The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 60.
18
PVDD
P
PLL Supply Voltage (1.8 V).
19, 23, 24
AIN1 to AIN3
I
Analog Video Input Channels.
20
VREFP
O
Internal Voltage Reference Output. See Figure 60 for recommended output circuitry.
21
VREFN
O
Internal Voltage Reference Output. See Figure 60 for recommended output circuitry.
22
AVDD
P
Analog Supply Voltage (1.8 V).
25
RESET
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7180 circuitry.
26
ALSB
I
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.
27
SDATA
I/O
I2C Port Serial Data Input/Output Pin.
28
SCLK
I
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
31
VS/FIELD
O
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
32
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
EPAD (EP)
The exposed pad must be connected to GND.
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