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參數(shù)資料
| 型號： | EVAL-ADF4360-9EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR ADF4360-9 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-9 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 360MHz，1.6MHz PFD |
| 已供物品： | 板 |
| 其它名稱： | Q5254840 |
Data Sheet
ADF4360-9
Rev. C | Page 21 of 24
GSM TEST CLOCK
Figure 30 shows the ADF4360-9 used to generate three different
frequencies at DIVOUT. The frequencies required are 45 MHz,
80 MHz, and 95 MHz. This is achieved by generating 360 MHz,
320 MHz, and 380 MHz and programming the correct A divider
ratio. Because a 50% duty cycle is required, the A/2 DIVOUT
mode is selected. This means that A values of 4, 2, and 2 are
selected, respectively, for each of the output frequencies
previously mentioned.
The low-pass filter was designed using ADIsimPLL for a
channel spacing of 1 MHz and an open-loop bandwidth of
40 kHz. Larger PFD frequencies can be used to reduce in-band
noise and, therefore, rms jitter. However, for the purposes of
this example, 1 MHz is used. The measured rms jitter from this
circuit at each frequency is less than 1.5 ps.
Two 21 nH inductors are required for the specified frequency
range. The reference frequency is from a 20 MHz TCXO from
Fox; therefore, an R value of 20 is programmed. Taking into
account the high PFD frequency and its effect on the band
select logic, the band select clock divider is enabled. In this case,
a value of 8 is chosen. A very simple shunt resistor and dc-blocking
capacitor complete the RF output stage. Because these outputs
are not used, they are terminated in 50 resistors. This is
recommended for circuit stability. Leaving the RF outputs
open is not recommended.
The CMOS level output frequency is available at DIVOUT. If
the frequency has to drive a low impedance load, a buffer is
recommended.
SPI
-C
O
M
PA
TIB
LE
S
E
R
IA
L
BUS
ADF4360-9
VVCO
FOX
801BE-160
20MHz
VVCO
CPGND
AGND DGND L1 L2
RFOUTB
RFOUTA
CP
DIVOUT
1nF
150pF
21nH
470
21nH
470
56pF
51
100pF
1nF
10F
4.7k
5.6k
12k
RSET
CC
LE
DATA
CLK
REFIN
CN
VTUNE
AVDD
DVDD
LD
5
4
7
23
21
2
6
14
16
17
18
19
13
1
3
8
9
10
11
22
15
12
51
VVDD
LOCK
DETECT
07139-
027
20
24
Figure 30.GSM Test Clock
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