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參數(shù)資料
| 型號： | EVAL-ADF4360-8EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4360-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-8 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 120MHz，1MHz PFD |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4360-8BCPZ-ND - IC SYNTHESIZER VCO 24-LFCSP ADF4360-8BCPZRL7TR-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-8BCPZRL-ND - IC SYNTHESIZER VCO 24LFCSP |
| 其它名稱： | Q4990657 |
ADF4360-8
Rev. A | Page 17 of 24
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-8 after
power-up is
1.
R counter latch
2.
Control latch
3.
N counter latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AVDD, DVDD, VVCO, and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-8 during initial power-up to settle.
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-8 may not achieve lock. If the recom-
mended interval is inserted, and the N counter latch is pro-
grammed, the band select logic can choose the correct fre-
quency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the CN pin (Pin 14). This capacitor is used to
reduce the close-in noise of the ADF4360-8 VCO. The
recommended value of this capacitor is 10 F. Using this value
requires an interval of ≥15 ms between the latching in of the
control latch bits and latching in of the N counter latch bits. If a
shorter delay is required, the capacitor can be reduced. A slight
phase noise penalty is incurred by this change, which is further
explained in Table 10.
Table 10. CN Capacitance vs. Interval and Phase Noise
CN Value
Recommended Interval
Between Control Latch
and N Counter Latch
Open-Loop Phase Noise
@ 10 kHz Offset
(L1 and L2 = 18.0 nH)
Open-Loop Phase Noise
@ 10 kHz Offset
(L1 and L2 = 110.0 nH)
Open-Loop Phase Noise
@ 10 kHz Offset
(L1 and L2 = 560.0 nH)
10 F
≥15 ms
100 dBc/Hz
97 dBc/Hz
99 dBc/Hz
440 nF
≥ 600 s
99 dBc/Hz
96 dBc/Hz
98 dBc/Hz
CLOCK
POWER-UP
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
04763-033
Figure 21. ADF4360-8 Power-Up Timing
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