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參數(shù)資料
| 型號(hào)： | EVAL-ADF4360-8EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4360-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-8 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 120MHz，1MHz PFD |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4360-8BCPZ-ND - IC SYNTHESIZER VCO 24-LFCSP ADF4360-8BCPZRL7TR-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-8BCPZRL-ND - IC SYNTHESIZER VCO 24LFCSP |
| 其它名稱： | Q4990657 |
ADF4360-8
Rev. A | Page 11 of 24
Lock Detect
MUXOUT can be programmed for one type of lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase error
on three consecutive phase detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
INPUT SHIFT REGISTER
The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
C2
C1
Data Latch
0
Control Latch
0
1
R Counter
1
0
N Counter (B)
1
Test Modes Latch
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 19, to allow a wide frequency range to
be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is
1.
R counter latch
2.
Control latch
3.
N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
0
1.0
0.5
2.5
2.0
1.5
3.5
3.0
80
85
90
100
95
105
115
110
FREQUENCY (MHz)
V
TUNE
(V
)
04763-019
Figure 19. Frequency vs. VTUNE, ADF4360-8, L1 and L2 = 270 nH
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8,
and is controlled by the BSC1 bit and the BSC2 bit in the R
counter latch. Where the required PFD frequency exceeds
1 MHz, the divide ratio should be set to allow enough time for
correct band selection.
After band selection, normal PLL action resumes. The value of
KV is determined by the value of inductors used (see the
Choosing the Correct Inductance Value section). The ADF4360
family contains linearization circuitry to minimize any variation
of the product of ICP and KV.
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
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