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參數(shù)資料
| 型號： | EVAL-ADF4360-1EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4360-1 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-1 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 2.25GHz，200kHz PFD |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4360-1BCPZ-ND - IC SYNTHESIZER VCO 24-LFCSP ADF4360-1BCPZRL7-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-1BCPZRL-ND - IC SYNTHESIZER VCO 24LFCSP |
| 其它名稱： | Q4875592 Q5594761 |
Data Sheet
ADF4360-1
Rev. C | Page 11 of 24
After band select, normal PLL action resumes. The nominal value
of KV is 57 MHz/V or 28 MHZ/V if divide-by-2 operation has been
selected (by programming DIV2 [DB22], high in the N counter
latch). The ADF4360 family contains linearization circuitry to min-
imize any variation of the product of ICP and KV.
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are con-
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 15. To allow
the user to optimize the power dissipation versus the output
power requirements, the tail current of the differential pair is
programmable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of 13 dBm, 10.5 dBm,
8 dBm, and 6 dBm, respectively, using a 50 resistor to VDD
and ac coupling into a 50 load. Alternatively, both outputs
can be combined in a 1 + 1:1 transformer or a 180° microstrip
coupler (see the Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
mute-till-lock detect (MTLD) bit in the control latch.
VCO
RFOUTA
RFOUTB
BUFFER/
DIVIDE BY 2
04414-015
Figure 15. Output Stage ADF4360-1
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| EVAL-ADF4360-2EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR ADF4360-2 |
| EVAL-ADF4360-2EBZ1 | 功能描述:BOARD EVALUATION FOR ADF4360-2 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADF4360-3EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR ADF4360-3 |
| EVAL-ADF4360-4EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
| EVAL-ADF4360-4EBZ1 | 制造商:Analog Devices 功能描述:Evaluation Board Integrated Synthesizer And VCO 制造商:Analog Devices 功能描述:Evaluation Board I.C. |
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