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參數(shù)資料
| 型號(hào)： | EVAL-ADF4106EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4106 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4106 |
| 主要屬性： | 單路整數(shù)-N PLL |
| 次要屬性： | 6GHz 圖形用戶(hù)界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4106BCPZ-ND - IC PLL FREQ SYNTHESIZER 20LFCSP ADF4106BRUZ-R7-ND - IC PLL FREQ SYNTHESIZER 16TSSOP ADF4106BCPZ-R7-ND - IC PLL FREQ SYNTHESIZER 20LFCSP ADF4106BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 20LFCSP ADF4106BRUZ-RL-ND - IC PLL FREQ SYNTHESIZER 16TSSOP ADF4106BRUZ-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4106BRU-REEL7-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4106BRU-REEL-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4106BRU-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP |
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ADF4106
Data Sheet
Rev. E | Page 10 of 24
GENERAL DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is a normally open switch.
When power-down is initiated, SW3 is closed and SW1 and
SW2 are opened. This ensures that there is no loading of the
REFIN pin on power-down.
02720-017
100k
NC
REFIN
NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
Figure 17. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
02720-
018
500
1.6V
500
AGND
RFINA
RFINB
AVDD
BIAS
GENERATOR
Figure 18. RF Input Stage
PRESCALER (P/P +1)
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A counter and
B counter. The prescaler is programmable. It can be set in soft-
ware to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value, and is given by (P2 P).
A COUNTER AND B COUNTER
The A counter and B CMOS counter combine with the dual
modulus prescaler to allow a wide ranging division ratio in the
PLL feedback counter. The counters are specified to work when
the prescaler output is 325 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.
Pulse Swallow Function
The A counter and B counter, in conjunction with the dual-
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is
R
REFIN
f
A
B
P
VCO
f
where:
fVCO is the output frequency of the external voltage controlled
oscillator (VCO).
P is the preset modulus of the dual-modulus prescaler
(8/9, 16/17, etc.).
B is the preset divide ratio of the binary 13-bit counter
(3 to 8191).
A is the preset divide ratio of the binary 6-bit swallow
counter (0 to 63).
fREFIN is the external reference frequency oscillator.
LOAD
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
13-BIT B
COUNTER
TO PFD
6-BIT A
COUNTER
N DIVIDER
MODULUS
CONTROL
N = BP + A
02720-
019
Figure 19. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
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