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參數(shù)資料
| 型號： | EVAL-ADF4106EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4106 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4106 |
| 主要屬性： | 單路整數(shù)-N PLL |
| 次要屬性： | 6GHz 圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4106BCPZ-ND - IC PLL FREQ SYNTHESIZER 20LFCSP ADF4106BRUZ-R7-ND - IC PLL FREQ SYNTHESIZER 16TSSOP ADF4106BCPZ-R7-ND - IC PLL FREQ SYNTHESIZER 20LFCSP ADF4106BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 20LFCSP ADF4106BRUZ-RL-ND - IC PLL FREQ SYNTHESIZER 16TSSOP ADF4106BRUZ-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4106BRU-REEL7-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4106BRU-REEL-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4106BRU-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP |
ADF4106
Data Sheet
Rev. E | Page 20 of 24
INTERFACING
The ADF4106 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits clocked into the input
register on each rising edge of CLK are transferred to the
appropriate latch. See Figure 2 for the timing diagram and
Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate for the device is 833 kHz,
or one update every 1.2 s. This is certainly more than adequate
for systems that have typical lock times in hundreds of
microseconds.
ADuC812 Interface
Figure 23 shows the interface between the ADF4106 and the
ADuC812 MicroConverter. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
is written, the LE input should be brought high to complete
the transfer.
On first applying power to the ADF4106, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control
power-down (CE input) and to detect lock (MUXOUT
configured as lock detect and polled by the port input).
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that
the maximum rate at which the output frequency can be
changed is 166 kHz.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
MOSI
ADF4106
SCLOCK
I/O PORTS
ADuC812
02720-028
Figure 23. ADuC812-to-ADF4106 Interface
ADSP2181 Interface
Figure 24 shows the interface between the ADF4106 and the
ADSP21xx digital signal processor (DSP). The ADF4106
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
MOSI
ADF4106
SCLOCK
I/O FLAGS
ADSP-21xx
TFS
02720-029
Figure 24. ADSP-21xx-to-ADF4106 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the LFCSP (CP-20) are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the LFCSP has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias may be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they
should be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter should be between 0.3 mm and 0.33 mm, and
the via barrel should be plated with 1 oz. copper to plug the via.
The user should connect the PCB thermal pad to AGND.
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