V
參數(shù)資料
型號： EVAL-AD5382EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 38/40頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5382
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 32
位數(shù)： 14
采樣率（每秒）： 125k
數(shù)據(jù)接口： DSP，I²C，MICROWIRE?，并行，QSPI?，SPI?
設(shè)置時間： 8µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5382
其它名稱： Q4391457
Data Sheet
AD5382
Rev. C | Page 7 of 40
Parameter
AD5382-31
Unit
Test Conditions/Comments
LOGIC OUTPUTS (BUSY, SDO)3
VOL, Output Low Voltage
0.4
V max
Sinking 200 A
VOH, Output High Voltage
DVDD – 0.5
V min
Sourcing 200 A
High Impedance Leakage Current
±1
A max
SDO only
High Impedance Output Capacitance
5
pF typ
SDO only
LOGIC OUTPUT (SDA)3
VOL, Output Low Voltage
0.4
V max
ISINK = 3 mA
0.6
V max
ISINK = 6 mA
Three-State Leakage Current
±1
A max
Three-State Output Capacitance
8
pF typ
POWER REQUIREMENTS
AVDD
2.7/3.6
V min/max
DVDD
2.7/5.5
V min/max
Power Supply Sensitivity3
Midscale/ΑVDD
–85
dB typ
AIDD
0.375
mA/channel max
Outputs unloaded; boost off; 0.25 mA/channel typ
0.475
mA/channel max
Outputs unloaded; boost on; 0.325 mA/channel typ
DIDD
1
mA max
VIH = DVDD VIL = DGND
AIDD (Power-Down)
20
A max
Typically 100 nA
DIDD (Power-Down)
20
A max
Typically 1 A
Power Dissipation
39
mW max
Outputs unloaded; boost off; AVDD = DVDD = 3 V
1
AD5382-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.
2
Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.
3
Guaranteed by characterization, not production tested.
4
Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded
accuracy specifications.
AC CHARACTERISTICS1
AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND= 0 V.
Table 4.
Parameter
All
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time2
1/4 scale to 3/4 scale change settling to ±1 LSB
3
s typ
8
s max
Slew Rate2
1.5
V/s typ
Boost mode off, CR11 = 0
2.5
V/s typ
Boost mode on, CR11 = 1
Digital-to-Analog Glitch Energy
12
nV-s typ
Glitch Impulse Peak Amplitude
15
mV typ
DAC-to-DAC Crosstalk
1
nV-s typ
Digital Crosstalk
0.8
nV-s typ
Digital Feedthrough
0.1
nV-s typ
Effect of input bus activity on DAC output under test
Output Noise 0.1 Hz to 10 Hz
15
V p-p typ
External reference, midscale loaded to DAC
40
V p-p typ
Internal reference, midscale loaded to DAC
Output Noise Spectral Density
at 1 kHz
150
nV/√Hz typ
at 10 kHz
100
nV/√Hz typ
1
Guaranteed by design and characterization, not production tested.
2
The slew rate can be programmed via the current boost control bit (CR11) in the AD5382 control register.
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