參數(shù)資料
型號(hào)： EVAL-AD5382EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/40頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5382
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 32
位數(shù)： 14
采樣率（每秒）： 125k
數(shù)據(jù)接口： DSP，I²C，MICROWIRE?，并行，QSPI?，SPI?
設(shè)置時(shí)間： 8µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5382
其它名稱： Q4391457
Data Sheet
AD5382
Rev. C | Page 33 of 40
APPLICATION INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5382 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5382 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only, a star ground
point established as close to the device as possible.
For supplies with multiple pins (AVDD, DVDD), these pins
should be tied together. The AD5382 should have ample supply
bypassing of 10 F in parallel with 0.1 F on each supply,
located as close as possible to the package and ideally right up
against the device. The 10 F capacitors are the tantalum bead
type. The 0.1 F capacitor should have low effective series
resistance (ESR) and effective series inductance (ESI), like the
common ceramic types that provide a low impedance path to
ground at high frequencies, to handle transient currents due to
internal logic switching.
The power supply lines of the AD5382 should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the DIN and SCLK lines helps reduce crosstalk between
them. This is not required on a multilayer board because there
is a separate ground plane, but separating the lines helps. It is
essential to minimize noise on the VIN and REFIN lines.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to
each other. This reduces the effects of feedthrough through
the board. A microstrip technique is by far the best, but is
not always possible with a double-sided board. In this tech-
nique, the component side of the board is dedicated to the
ground plane while signal traces are placed on the solder side.
TYPICAL CONFIGURATION CIRCUIT
Figure 38 shows a typical configuration for the AD5382-5
when configured for use with an external reference. In the
circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins
are tied together to a common AGND. AGND and DGND are
connected together at the AD5382 device. On power-up, the
AD5382 defaults to external reference operation. All AVDD
lines are connected together and driven from the same 5 V
source. It is recommended to decouple close to the device
with a 0.1 F ceramic and a 10 F tantalum capacitor.
In this application, the reference for the AD5382-5 is provided
externally from either an ADR421 or ADR431 2.5 V reference.
Suitable external references for the AD5382-3 include the
ADR280 1.2 V reference. The reference should be decoupled at
the REFOUT/REFIN pin of the device with a 0.1 F capacitor.
03733-039
ADR431/
ADR421
AD5382-5
AVDD
DVDD
SIGNAL_GND
DAC_GND
DGND
VOUT31
VOUT0
AGND
REFOUT/REFIN
REFGND
0.1
F
10
F
0.1
F
0.1
F
AVDD
DVDD
Figure 38. Typical Configuration with External Reference
Figure 39 shows a typical configuration when using the internal
reference. On power-up, the AD5382 defaults to an external
reference; therefore, the internal reference needs to be config-
ured and turned on via a write to the AD5382 control register.
Control Register Bit CR12 allows the user choose the reference
value; Bit CR 10 is used to select the internal reference. It is
recommended to use the 2.5 V reference when AVDD = 5 V,
and the 1.25 V reference when AVDD = 3 V.
03733-040
AD5382
AVDD
DVDD
SIGNAL_GND
DAC_GND
DGND
VOUT31
VOUT0
AGND
REFOUT/REFIN
REFGND
0.1
F
10
F
0.1
F
0.1
F
AVDD
DVDD
Figure 39. Typical Configuration with Internal Reference
Digital connections have been omitted for clarity. The AD5382
contains an internal power-on reset circuit with a 10 ms brown-
out time. If the power supply ramp rate exceeds 10 ms, the user
should reset the AD5382 as part of the initialization process to
ensure the calibration data is loaded correctly into the device.
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