參數(shù)資料
型號： EVAL-AD5382EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/40頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5382
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 32
位數(shù)： 14
采樣率（每秒）： 125k
數(shù)據(jù)接口： DSP，I²C，MICROWIRE?，并行，QSPI?，SPI?
設(shè)置時(shí)間： 8µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5382
其它名稱： Q4391457
AD5382
Data Sheet
Rev. C | Page 22 of 40
Table 13. Gain Data Format (REG1 = 0, REG0 = 1)
DB13 to DB0
Gain Factor
11
1111
1110
1
10
1111
1110
0.75
01
1111
1110
0.5
00
1111
1110
0.25
00
0000
0
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
The AD5382 contains a number of special function registers
(SFRs), as outlined in Table 14. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using Address Bits A4 to A0.
Table 14. SFR Register Functions (REG1 = 0, REG0 = 0)
R/W
A4
A3
A2
A1
A0
Function
X
0
NOP (No Operation)
0
1
Write Clear Code
0
1
0
Soft Clear
0
1
0
Soft Power-Down
0
1
0
1
Soft Power-Up
0
1
0
Control Register Write
1
0
1
0
Control Register Read
0
1
0
1
0
Monitor Channel
0
1
Soft Reset
SFR COMMANDS
NOP (No Operation)
REG1 = REG0 = 0, A4–A0 = 00000
Performs no operation but is useful in serial readback mode to
clock out data on DOUT for diagnostic purposes. BUSY pulses
low during a NOP operation.
Write Clear Code
REG1 = REG0 = 0, A4–A0 = 00001
DB13–DB0 = Contain the clear code data
Bringing the CLR line low or exercising the soft clear function
loads the contents of the DAC registers with the data contained
in the user-configurable Clear register, and sets VOUT0 to
VOUT31 accordingly. This can be very useful for setting up a
specific output voltage in a clear condition. It is also beneficial
for calibration purposes; the user can load full scale or zero
scale to the clear code register and then issue a hard-ware or
software clear to load this code to all DACs, removing the
need for individual writes to each DAC. Default on power-up
is all zeros.
Soft Clear
REG1 = REG0 = 0, A4–A0 = 00010
DB13–DB0 = Don’t Care
Executing this instruction performs a software clear, which is
functionally the same as that provided by the external CLR pin.
The DAC outputs are loaded with the data in the Clear Code.
register (Table 14). It takes 35 s to fully execute the Soft Clear
and is indicated by the BUSY low time.
Soft Power-Down
REG1 = REG0 = 0, A4–A0 = 01000
DB13–DB0 = Don’t Care
Executing this instruction performs a global power-down
feature that puts all channels into a low power mode that
reduces the analog supply current to 2 A max and the digi-
tal current to 20 A max. In power-down mode, the output
amplifier can be configured as a high impedance output or
provide a 100 k load to ground. The contents of all internal
registers are retained in power-down mode. No register can
be written to while in power-down.
Soft Power-Up
REG1 = REG0 = 0, A4–A0 = 01001
DB13–DB0 = Don’t Care
This instruction is used to power up the output amplifiers and
the internal reference. The time to exit power-down is 8 s.
The hardware power-down and software functions are
internally combined in a digital OR function.
Soft RESET
REG1 = REG0 = 0, A4–A0 = 01111
DB13–DB0 = Don’t Care
This instruction is used to implement a software reset.
All internal registers are reset to their default values, which
correspond to m at full scale and c at zero. The contents of
the DAC registers are cleared, setting all analog outputs to 0 V.
The soft reset activation time is 135 s max.
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