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參數(shù)資料
| 型號(hào)： | EVAL-AD1974AZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1974 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 4 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1.9 Vrms |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD1974 |
| 已供物品： | 板 |
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Data Sheet
AD1974
Rev. D | Page 15 of 24
ALRCLK
ABCLK
FOUR ADC CHANNELS OF
THE SECOND IC IN THE CHAIN
FOUR ADC CHANNELS OF
THE FIRST IC IN THE CHAIN
ADCL1
ADCR1
ADCL2
ADCR2
ADCL1
ADCR1
ADCL2
ADCR2 UNUSED
UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
ASDATA1 (TDM_OUT
OF THE SECOND AD1974
IN THE CHAIN)
ADCL1
ADCR1
ADCL2
ADCR2
ASDATA2 (TDM_IN
OF THE SECOND AD1974
IN THE CHAIN)
32 BITS
MSB
DSP
SECOND
AD1974
FIRST
AD1974
06
61
4-
05
7
ALRCLK
ABCLK
ASDATA
ALRCLK
ABCLK
ASDATA
ALRCLK
ABCLK
ASDATA
LSB
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
RIGHT JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I2S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
ALRCLK
ABCLK
ASDATA
LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
fS EXCEPT FOR DSP MODE WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB
1/
fS
06
61
4-
0
13
Figure 11. Stereo Serial Modes
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