參數(shù)資料
型號(hào)： EVAL-AD1974AZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD1974
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 4
位數(shù)： 24
采樣率（每秒）： 192k
數(shù)據(jù)接口： 串行
輸入范圍： 1.9 Vrms
工作溫度： -40°C ~ 125°C
已用 IC / 零件： AD1974
已供物品： 板
Data Sheet
AD1974
Rev. D | Page 13 of 24
TDM MODES
The AD1974 serial ports also have several different TDM serial
data modes. The first and most commonly used configuration
is shown in Figure 6 where the ADC serial port outputs one
data stream consisting of four on-chip ADCs followed by four
unused slots. In this mode, ABCLK is set to 256 fS (8-channel
TDM mode).
The I/O pins of the serial ports are defined according to the
serial mode selected. For a detailed description of the function
of each pin in TDM and AUX Modes, see Table 12.
The AD1974 allows system configurations with more than four
ADC channels (see Figure 7 and Figure 8) that use 8 ADCs and
16 ADCs. In this mode, four AUX channel slots in the TDM out-
put stream follow four on-chip ADC channel slots. It should be
noted that due to the high ABCLK frequency, this mode is
available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
MSB
MSB–1
MSB–2
ADATA
ABCLK
ALRCLK
UNUSED UNUSED UNUSED UNUSED
ALRCLK
ABCLK
ADATA
256 BCLKs
32 BCLKs
06614
-016
Figure 6. ADC TDM (8-Channel I2S Mode)
Table 12. Pin Function Changes in TDM and AUX Modes
Pin Name
Stereo Mode
TDM Mode
AUX Mode
ASDATA1
ADC1 data output
ADC TDM data output
ADCTDM data output
ASDATA2
ADC2 data output
ADC TDM data input
Not used (float)
AUXDATA1
Not used (ground)
AUXDATA in 1 (from external ADC1)
AUXDATA2
Not used (ground)
AUXDATA in 2 (from external ADC2)
ALRCLK
ADC LRCLK input/output
ADC TDM frame sync input/output
ADCTDM frame sync input/output
ABCLK
ADC BCLK input/output
ADC TDM BCLK input/output
ADCTDM BCLK input/output
AUXLRCLK
Not used (ground)
AUXLRCLK input/output
AUXBCLK
Not used (ground)
AUXBCLK input/output
ABCLK
ALRCLK
AUXLRCLK
(AUX PORT)
ASDATA1
(TDM_OUT)
AUXBCLK
(AUX PORT)
AUXDATA1
(AUX1_IN)
AUXDATA2
(AUX2_IN)
ADCL1
ADCR1
ADCL2
ADCR2
AUXL1
AUXR1
AUXL2
AUXR2
FOUR-ON-CHIP DAC CHANNELS
32 BITS
LEFT
RIGHT
MSB
FOUR-AUX ADC CHANNELS
06
61
4-
0
50
Figure 7. 8-Channel AUX ADC Mode
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