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參數(shù)資料
| 型號： | EVAL-AD1974AZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD1974 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 4 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1.9 Vrms |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD1974 |
| 已供物品： | 板 |
Data Sheet
AD1974
Rev. D | Page 21 of 24
Bit
Value
Function
Description
6:5
00
Stereo
Serial format
01
TDM (daisy chain)
10
ADC AUX mode (TDM-coupled)
11
Reserved
7
0
Latch in midcycle (normal)
BCLK active edge (TDM_IN)
1
Latch in at end of cycle (pipeline)
Table 23. ADC Control 2
Bit
Value
Function
Description
0
50/50 (allows 32-/24-/20-/16-BCLK per channel)
LRCLK format
1
Pulse (32-BCLK/channel)
1
0
Drive out on falling edge (DEF)
BCLK polarity
1
Drive out on rising edge
2
0
Left low
LRCLK polarity
1
Left high
3
0
Slave
LRCLK master/slave
1
Master
5:4
00
64
BCLKs per frame
01
128
10
256
11
512
6
0
Slave
BCLK master/slave
1
Master
7
0
ABCLK pin
BCLK source
1
Internally generated
ADDITIONAL MODES
The AD1974 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 15 for an example of an ADC TDM data transmission
mode that does not require high speed ABCLK. This configura-
tion is applicable when the AD1974 master clock is generated
by the PLL with the ALRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the AD1974 in
cases of high speed TDM data transmission, the AD1974 can
latch in the data using the falling edge of ABCLK. This effec-
tively dedicates the entire BCLK period to the setup time. This
mode is useful in cases where the source has a large delay time
in the serial data driver. Figure 16 shows this pipeline mode of
data transmission.
ALRCLK
INTERNAL
ABCLK
ASDATA2
ALRCLK
INTERNAL
ABCLK
ASDATA2
32 BITS
06
61
4-
0
5
9
Figure 15. Serial ADC Data Transmission in TDM Format Without ABCLK
(Applicable Only If PLL Locks to ALRCLK)
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