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參數(shù)資料
| 型號(hào)： | EVAL-AD1974AZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1974 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 4 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1.9 Vrms |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD1974 |
| 已供物品： | 板 |
Data Sheet
AD1974
Rev. D | Page 19 of 24
Table 17. PLL and Clock Control 1
Bit
Value
Function
Description
0
PLL clock
AUXPORT clock source select
1
MCLK
1
0
PLL clock
ADC clock source select
1
MCLK
2
0
Enabled
On-chip voltage reference
1
Disabled
3
0
Not locked
PLL lock indicator (read only)
1
Locked
7:4
0000
Reserved
AUXPORT CONTROL REGISTERS
Table 18.
AUXPORT Control 0
Bit
Value
Function
Description
0
Reserved
1
Reserved
2:1
00
32 kHz/44.1 kHz/48 kHz
Sample rate
01
64 kHz/88.2 kHz/96 kHz
10
128 kHz/176.4 kHz/192 kHz
11
Reserved
5:3
000
1
AUXDATA delay (AUXBCLK periods)
001
0
010
8
011
12
100
16
101
Reserved
110
Reserved
111
Reserved
7:6
00
Stereo (normal)
Serial format
01
Reserved
10
ADC AUX mode (ADC-, TDM-coupled)
11
Reserved
Table 19. AUXPORT Control 1
Bit
Value
Function
Description
0
Reserved
1
Reserved
2:1
00
64 (two channels)
AUXBCLKs per frame
01
Reserved
10
Reserved
11
Reserved
3
0
Left low
AUXLRCLK polarity
1
Left high
4
0
Slave
AUXLRCLK master/slave
1
Master
5
0
Slave
AUXBCLK master/slave
1
Master
6
0
AUXBCLK pin
AUXBCLK source
1
Internally generated
7
0
Normal
AUXBCLK polarity
1
Inverted
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