參數(shù)資料
型號(hào)： EPVP6800
廠商： ELAN Microelctronics Corp .
英文描述： VFD Controller
中文描述： 變頻控制器
文件頁數(shù)： 34/47頁
文件大?。?/td> 325K
代理商： EPVP6800
ePVP6800
VFD Controller
28 of 47
11. 28.2004
(V1.23)
This specification is subject to change without further notice.
7.7.4 Wake-up from IDLE Mode
1. WDT time out
2. External interrupt
3. Internal interrupt like counters
All these cases requires you to enable the circuit before entering IDLE mode. All the registers values
are preserved when "SLEP" instruction is executed and restored after wake-up.
During execution of case 2 or 3, controller will wake up and jump to address 0x08 for interruption
sub-routine. After performing the sub-routine ("RETI" instruction), the program will jump to the next
instruction following the "SLEP" instruction.
7.8 nterrupts
RD, RF are the interrupt status registers which record the interrupt request in flag bit. IOCD,& IOCF
are their interrupt mask registers respectively. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the
next instruction to be fetched from address 008H. Once in the interrupt service routine, the source of
the interrupt can be determined by polling the flag bits in their respective (RD, RE, and RF) registers.
The interrupt flag bit must be cleared in the software before leaving the interrupt service routine and
enabling interrupts to avoid recursive interrupts.
7.9 nstruction Set
The Instruction set has the following features
:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O register can be treated as a general register. That is, the same instruction can operates on
I/O register.
The symbol "R" represents a register designator which specifies which one of the 64 registers
(including operational registers and general purpose registers) is to be utilized by the instruction. Bits
6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects
the number of the bit located in the Register "R,” and affected by the operation. "k'' represents an 8 or
10-bit constant or literal value.
Instruction Binary
HEX
Mnemonic
Operation
Status
Affected
Instruction
Cycle
0 0000 0000 0000
0000
NOP
No Operation
None
1
0 0000 0000 0001
0001
DAA
Decimal Adjust A
C
1
0 0000 0000 0010
0002
CONTW
A
→
CONT
None
1
0 0000 0000 0011
0003
SLEP
0
→
WDT, Stop oscillator
T,P
1
0 0000 0000 0100
0004
WDTC
0
→
WDT
T,P
1
0 0000 0000 rrrr
000r
IOW R
A
→
IOCR
None
1
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
1
0 0000 0001 0001
0011
DISI
Disable Interrupt
None
1
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