
ePVP6800
VFD Controller
This specification is subject to change without further notice.
11.28.2004 (V123)
17 of 47
7.2.15 RE (Interrupt Flags, Wake-up)
a) PAGE 0 (Interrupt Flags, Wake-up Control Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
/WUPC3
/WUPC2
/WUPC1
/WUPC0
-
-
-
-
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 (/WUPC0)
:
PORTC0 wake-up control,
0/1
disable/enable PC0 pin wake-up function
Bit 1 (/WUPC1)
:
PORTC1 wake-up control, 0/1
disable/enable PC1 pin wake-up function
Bit 2 (/WUPC2)
:
PORTC2 wake-up control,
0/1
disable/enable PC2 pin wake-up function
Bit 3 (/WUPC3)
:
PORTC3 wake-up control,
0/1
disable/enable PC3 pin wake-up function
Bit 4 (-)
:
Not used
Bit 5 (-)
:
Not used
Bit 6 (-)
:
Not used
Bit 7(-)
:
Not used
7.2.16 RF (Interrupt Flags)
a) PAGE 0 (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT4
INT3
INT2
INT1
IR
CNT2
CNT1
TCIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NOTE:
"1" means interrupt request, "0" means non-interrupt
Bit 0 (TCIF)
:
TCC timer overflow interrupt flag, Set when TCC timer overflows.
Bit 1 (CNT1)
:
Counter1 timer overflow interrupt flag. Set when Counter1 timer overflows.
Bit 2 (CNT2)
:
Counter2 timer overflow interrupt flag. Set when Counter2 timer overflows.
Bit 3 (IR)
:
External INT pin interrupt flag. If PORT90 contains a falling /rising edge
(controlled by CONT register) trigger signal, CPU will set this bit.
Bit 4 (INT1)
:
External INT1 pin interrupt flag, If PORT91 contains a falling edge trigger
signal, CPU will set this bit.
Bit 5(INT2)
:
External INT2 pin interrupt flag. If PORT92 has a falling edge trigger
signal, CPU will set this bit.
Bit 6 : (INT3)
:
External INT3 pin interrupt flag. If PORT93 has a falling edge trigger
signal, CPU will set this bit.
Bit 7(INT4)
:
External IR interrupt flag. If PORT94 has a falling edge trigger signal, CPU
will set this bit.