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參數(shù)資料
| 型號： | EPVP6800 |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | VFD Controller |
| 中文描述： | 變頻控制器 |
| 文件頁數(shù)： | 25/47頁 |
| 文件大小： | 325K |
| 代理商： | EPVP6800 |
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ePVP6800
VFD Controller
This specification is subject to change without further notice.
11.28.2004 (V123)
19 of 47
Bit 3 (PAB)
:
Prescaler assignment bit
0/1
TCC/WDT
When in WDT mode (Bit 3 = 1), the prescaler is cleared by the WDTC and SLEP
instructions. Likewise, when in TCC mode (Bit 3 = 0), the prescaler will can NOT be
cleared by SLEP instructions.
An 8-bit counter is provided as prescaler for the TCC or WDT. The prescaler is
available for the TCC only or for the WDT only at a given time.
An 8 bit counter is made available for TCC or WDT as determined by the status of
Bit 3 (PAB) of the CONT register.
Both TCC and prescaler are cleared each time a write to TCC instruction is
executed. (See the table above for the prescaler ratio under CONT register and
Fig.5 below for the TCC/WDT block diagram.)
Bit 4 (RETBK)
:
Return value backup control for interrupt routine
0/1
disable/enable
When this bit is set to 1, the CPU will store ACC, R3 status, and R5 PAGE 1
automatically after an interrupt is triggered. It will be restored after instruction RETI.
When this bit is set to 0, you need to store ACC, R3, and R5 PAGE 1 in you
program.
Bit 5 (TS)
:
TCC signal source
0
internal instruction cycle clock
timing = ( 2 / system clock) * prescaler* (256 – count vaule)
1
16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 – count vaule)
timing = (2/Fosc) * Prescaler * (256 – count vaule)
Bit 6 (INT)
:
INT enable flag
0
interrupt masked by DISI or hardware interrupt
1
interrupt enabled by ENI/RETI instructions
Bit 7 (P90EG)
:
Interrupt edge type of P90
0
P90 interruption source is a rising edge signal.
1
P90 interruption source is a falling edge signal.
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