參數(shù)資料
型號(hào): EPC4
廠商: Altera Corporation
英文描述: Configuration Devices for SRAM-Based LUT Devices
中文描述: 配置SRAM器件基于LUT的器件
文件頁(yè)數(shù): 34/36頁(yè)
文件大小: 283K
代理商: EPC4
34
Altera Corporation
Configuration Devices for SRAM-based LUT Devices Data Sheet
Revision
History
The information contained in the
Configuration Devices for SRAM-Based
LUT Devices Data Sheet
version 12.1 supersedes information published in
pervious versions. The following changes were made to the
Configuration
Devices for SRAM-Based LUT Devices Data Sheet
version 12.1:
Updated
Table 2
.
Updated notes to
Figures 4
,
5
, and
6
.
Added APEX 20KE device diagrams to
Figures 4
and
6
.
Table 24. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 &
EPC1064V Devices
Symbol
Parameter
Conditions
EPC1064V
EPC1064
EPC1213
EPC1
EPC1441
Unit
Min Max Min Max Min Max
t
OEZX
t
CSZX
t
CSXZ
t
CSS
t
CSH
t
DSU
t
DH
t
CO
t
CK
f
CK
t
CL
t
CH
t
XZ
t
OEW
t
CASC
t
CKXZ
t
CEOUT
OE
high to
DATA
output enabled
75
50
50
ns
nCS
low to
DATA
output enabled
75
50
50
ns
nCS
high to
DATA
output disabled
75
50
50
ns
nCS
low setup time to first
DCLK
rising edge
150
100
50
ns
nCS
low hold time after
DCLK
rising edge
0
0
0
ns
Data setup time before rising edge on
DCLK
75
50
50
ns
Data hold time after rising edge on
DCLK
0
0
0
ns
DCLK
to
DATA
out delay
100
75
75
ns
Clock period
240
160
100
ns
Clock frequency
4
6
8
MHz
DCLK
low time
120
80
50
ns
DCLK
high time
120
80
50
ns
OE
low or
nCS
high to
DATA
output disabled
75
50
50
ns
OE
pulse width to guarantee counter reset
150
100
100
ns
Last
DCLK
+ 1 to
nCASC
low delay
90
60
50
ns
Last
DCLK
+ 1 to
DATA
tri-state delay
75
50
50
ns
nCS
high to
nCASC
high delay
150
100
100
ns
相關(guān)PDF資料
PDF描述
EPC8 Configuration Devices for SRAM-Based LUT Devices
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EPC1 Configuration Devices for SRAM-Based LUT Devices
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