參數(shù)資料
型號: EPC4
廠商: Altera Corporation
英文描述: Configuration Devices for SRAM-Based LUT Devices
中文描述: 配置SRAM器件基于LUT的器件
文件頁數(shù): 33/36頁
文件大?。?/td> 283K
代理商: EPC4
Altera Corporation
33
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 22. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &
EPC1441 Devices at 5.0-V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
CE
t
OEZX
t
CO
t
MCH
OE
high to first clock delay
200
ns
OE
high to data output enabled
50
ns
DCLK
to data out delay
20
ns
DCLK
high time for the first device in the
configuration chain
30
50
75
ns
t
MCL
DCLK
low time for the first device in the
configuration chain
30
50
75
ns
f
CK
t
SCH
t
SCL
t
CASC
t
CCA
f
CDOE
t
OEC
t
NRCAS
t
NRR
Clock frequency
6.7
10
16.7
MHz
DCLK
high time for subsequent devices
30
ns
DCLK
low time for subsequent devices
30
ns
CLK
rising edge to
nCASC
20
ns
nCS
to
nCASC
cascade delay
10
ns
CLK
to data enable/disable
20
ns
OE
low to
CLK
disable delay
20
ns
OE
low (reset) to
nCASC
delay
25
ns
OE
low time (reset) minimum
100
ns
Table 23. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &
EPC1441 Devices at 3.3-V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
CE
t
OEZX
t
CO
t
MCH
OE
high to first clock delay
300
ns
OE
high to data output enabled
80
ns
DCLK
to data out delay
30
ns
DCLK
high time for the first device in the
configuration chain
50
125
250
ns
t
MCL
DCLK
low time for the first device in the
configuration chain
50
125
250
ns
f
CK
t
SCH
t
SCL
t
CASC
t
CCA
f
CDOE
t
OEC
t
NRCAS
t
NRR
Clock frequency
2
4
10
MHz
DCLK
high time for subsequent devices
50
ns
DCLK
low time for subsequent devices
50
ns
CLK
rising edge to
nCASC
25
ns
nCS
to
nCASC
cascade delay
15
ns
CLK
to data enable/disable
30
ns
OE
low to
CLK
disable delay
30
ns
OE
low (reset) to
nCASC
delay
30
ns
OE
low time (reset) minimum
100
ns
相關PDF資料
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