參數(shù)資料
型號(hào)： EP4SGX70HF35I4N
廠商： Altera
文件頁(yè)數(shù)： 51/82頁(yè)
文件大?。?/td> 0K
描述： IC STRATIX IV FPGA 70K 1152FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 2904
邏輯元件/單元數(shù)： 72600
RAM 位總計(jì)： 7564880
輸入/輸出數(shù)： 488
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1152-BBGA
供應(yīng)商設(shè)備封裝： 1152-FBGA（27x27）
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–47
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Transceiver Datapath PCS Latency
f For more information about:
■
Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the Transceiver
■
PCIe mode PCS latency, refer to Figure 1-102 in the Transceiver Architecture in
■
XAUI mode PCS latency, refer to Figure 1-119 in the Transceiver Architecture in
■
GIGE mode PCS latency, refer to Figure 1-128 in the Transceiver Architecture in
■
SONET/SDH mode PCS latency, refer to Figure 1-136 in the Transceiver
■
SDI mode PCS latency, refer to Figure 1-141 in the Transceiver Architecture in Stratix
IV Devices chapter.
■
(OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the Transceiver
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn)
specifications.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
Clock Tree Specifications
Table 1–33 lists the clock tree specifications for Stratix IV devices.
Table 1–33. Clock Tree Performance for Stratix IV Devices
Performance
Unit
Symbol
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Global clock and
Regional clock
800
700
500
MHz
Periphery clock
550
500
MHz
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