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參數(shù)資料
| 型號： | EP2S60F484I4N |
| 廠商： | Altera |
| 文件頁數(shù)： | 755/768頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II FPGA 60K 484-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 20 |
| 系列： | Stratix® II |
| LAB/CLB數(shù)： | 3022 |
| 邏輯元件/單元數(shù)： | 60440 |
| RAM 位總計： | 2544192 |
| 輸入/輸出數(shù)： | 334 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA（23x23） |
| 配用： | 544-1700-ND - DSP KIT W/STRATIX II EP2S60N 544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N |
| 其它名稱： | 544-1910 EP2S60F484I4N-ND |
Altera Corporation
2–69
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Fast PLLs
Stratix II devices contain up to eight fast PLLs with high-speed serial
interfacing ability. Figure 2–45 shows a diagram of the fast PLL.
Figure 2–45. Stratix II Device Fast PLL
Notes to Figure 2–45:
(1)
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2)
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. Stratix II
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(3)
This signal is a differential I/O SERDES control signal.
(4)
Stratix II fast PLLs only support manual clock switchover.
(5)
If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
f
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of
the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information on enhanced and fast PLLs. See “High-Speed
Differential I/O with DPA Support” on page 2–96 for more information
on high-speed differential I/O support.
I/O Structure
The Stratix II IOEs provide many features, including:
■
Dedicated differential and single-ended I/O buffers
■
3.3-V, 64-bit, 66-MHz PCI compliance
■
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
■
Joint Test Action Group (JTAG) boundary-scan test (BST) support
■
On-chip driver series termination
■
On-chip parallel termination
■
On-chip termination for differential standards
■
Programmable pull-up during configuration
Charge
Pump
VCO
÷c1
8
4
8
Clock
Input
PFD
÷c0
÷m
Loop
Filter
Phase
Frequency
Detector
VCO Phase Selection
Selectable at each PLL
Output Port
Post-Scale
Counters
Global clocks
diffioclk1
load_en1
load_en0
diffioclk0
Regional clocks
to DPA block
Global or
regional clock (1)
Global or
regional clock (1)
÷c2
÷k
÷c3
÷n
4
Clock
Switchover
Circuitry (4)
Shaded Portions of the
PLL are Reconfigurable
(2)
(3)
(5)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2S60F672C3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 3022 LABs 492 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S60F672C3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 3022 LABs 492 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S60F672C4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 3022 LABs 492 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S60F672C4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 3022 LABs 492 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S60F672C5 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 3022 LABs 492 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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