Altera Corporation
1–37
July 2009
Stratix II Device Handbook, Volume 2
PLLs in Stratix II and Stratix II GX Devices
The switch-over state machine has two counters that count the edges of
the primary and the secondary clocks; counter0 counts the number of
inclk0
edges and counter1 counts the number of inclk1 edges. The
counters get reset to zero when the count values reach 1, 1; 1, 2; 2, 1; or 2,
2 for inclock0 and inclock1, respectively. For example, if counter0
counts two edges, its count is set to two and if counter1 counts two
edges before the counter0 sees another edge, they are both reset to 0. If
for some reason one of the counters counts to three, it means the other
clock missed an edge. The clkbad0 or clkbad1 signal goes high, and
the switchover circuitry signals a switch condition. See
Figure 1–19.
Figure 1–19. Clock-Edge Detection for Switchover
Manual Override
When using automatic switchover, you can switch input clocks by using
the manual override feature with the clkswitch input.
1
The manual override feature available in automatic clock
switchover is different from manual clock switchover.
Figure 1–20 shows an example of a waveform illustrating the switchover
feature when controlled by clkswitch. In this case, both clock sources
are functional and inclk0 is selected as the primary clock. clkswitch
goes high, which starts the switchover sequence. On the falling edge of
inclk0
, the counter’s reference clock, muxout, is gated off to prevent
any clock glitching. On the falling edge of inclk1, the reference clock
multiplexer switches from inclk0 to inclk1 as the PLL reference and
the activeclock signal changes to indicate which clock is selected as
primary and which is secondary.
The clkloss signal mirrors the clkswitch signal and activeclock
mirrors clksw in this mode. Since both clocks are still functional during
the manual switch, neither clk_bad signal goes high. Since the
inclk0
inclk1
clkbad0
Count of three on
single clock indicates
other missed edge.
Reset