5–84
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
Duty Cycle Distortion
1.8 V
150
265
85
ps
1.5-V LVCMOS
255
370
140
ps
SSTL-2 Class I
175
295
65
ps
SSTL-2 Class II
170
290
60
ps
SSTL-18 Class I
155
275
55
50
ps
SSTL-18 Class II
140
260
70
ps
1.8-V HSTL Class I
150
270
60
ps
1.8-V HSTL Class II
150
270
60
ps
1.5-V HSTL Class I
150
270
55
ps
1.5-V HSTL Class II
125
240
85
ps
1.2-V HSTL
240
360
155
ps
LVPECL
180
ps
(1)
(2)
The DCD specification is based on a no logic array noise condition.
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 1 of 2)
DDIO Column Output I/O
Standard
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
3.3-V LVTTL
440
495
170
160
ps
3.3-V LVCMOS
390
450
120
110
ps
2.5 V
375
430
105
95
ps
1.8 V
325
385
90
100
ps
1.5-V LVCMOS
430
490
160
155
ps
SSTL-2 Class I
355
410
85
75
ps
SSTL-2 Class II
350
405
80
70
ps
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Notes (1), (2)
DDIO Column Output I/O
Standard
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL
1.2-V
HSTL
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
1.2 V