Record the time to V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S15F672C5N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 78/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 15K 672-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 780
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 15600
RAM 浣嶇附瑷�(j矛)锛� 419328
杓稿叆/杓稿嚭鏁�(sh霉)锛� 366
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 672-BGA锛�27x27锛�
鍏跺畠鍚嶇ū锛� 544-1881
EP2S15F672C5N-ND
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�绗�756闋�绗�757闋�绗�758闋�绗�759闋�绗�760闋�绗�761闋�绗�762闋�绗�763闋�绗�764闋�绗�765闋�绗�766闋�绗�767闋�绗�768闋�
Altera Corporation
5鈥�23
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 5鈥�34 using the above equation. Figure 5鈥�4 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 5鈥�4. Output Delay Timing Reporting Setup Modeled by Quartus II
(1)
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2)
VCCPD is 3.085 V unless otherwise specified.
(3)
VCCINT is 1.12 V unless otherwise specified.
Figures 5鈥�5 and 5鈥�6 show the measurement setup for output disable and
output enable timing.
Output
Buffer
VTT
VCCIO
RD
Outputn
Outputp
RT
CL
RS
VMEAS
Output
GND
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
EP2S15F672I4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 780 LABs 366 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S15F672I4N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 780 LABs 366 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S180 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
EP2S180F1020C3 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 8970 LABs 742 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S180F1020C3GA 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix