Altera
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S15F672C5N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 75/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 15K 672-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 780
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 15600
RAM 浣嶇附瑷�(j矛)锛� 419328
杓稿叆/杓稿嚭鏁�(sh霉)锛� 366
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 672-BGA锛�27x27锛�
鍏跺畠鍚嶇ū锛� 544-1881
EP2S15F672C5N-ND
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5鈥�20
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
Power Consumption
Power
Consumption
Altera offers two ways to calculate power for a design: the Excel-based
PowerPlay Early Power Estimator power calculator and the Quartus II
PowerPlay Power Analyzer feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically
used prior to designing the FPGA in order to get an estimate of device
power. The Quartus II PowerPlay Power Analyzer provides better
quality estimates based on the specifics of the design after place-and-
route is complete. The Power Analyzer can apply a combination of user-
entered, simulation-derived and estimated signal activities which,
combined with detailed circuit models, can yield very accurate power
estimates.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
f
For more information about PowerPlay tools, refer to the PowerPlay Early
Power Estimator User Guide and the PowerPlay Early Power Estimator and
PowerPlay Power Analyzer chapters in volume 3 of the Quartus II
Handbook.
The PowerPlay Early Power Estimator is available on the Altera web site
specifications.
Timing Model
The DirectDriveTM technology and MultiTrackTM interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix II device densities and speed grades. This
section describes and specifies the performance, internal timing, external
timing, and PLL, high-speed I/O, external memory interface, and JTAG
timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
1
The timing numbers listed in the tables of this section are
extracted from the Quartus II software version 5.0 SP1.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary. Table 5鈥�33 shows the status of the
Stratix II device timing models.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
1N4148 DIODE SGL JUNC 100V 4.0NS DO-35
RMC35DRAH-S734 CONN EDGECARD 70POS .100 R/A PCB
ECC08DCAH CONN EDGECARD 16POS R/A .100 SLD
GCB15DHLN CONN EDGECARD 30POS .050 DIP SLD
GBM18DCWT CONN EDGECARD 36POS DIP .156 SLD
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EP2S15F672I4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 780 LABs 366 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
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EP2S180 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
EP2S180F1020C3 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 8970 LABs 742 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S180F1020C3GA 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix