鍨嬭櫉锛� | EP2S15F672C5N |
寤犲晢锛� | Altera |
鏂囦欢闋佹暩锛� | 115/768闋� |
鏂囦欢澶у皬锛� | 0K |
鎻忚堪锛� | IC STRATIX II FPGA 15K 672-FBGA |
鐢㈠搧鍩硅〒妯″锛� | Three Reasons to Use FPGA's in Industrial Designs |
妯欐簴鍖呰锛� | 10 |
绯诲垪锛� | Stratix® II |
LAB/CLB鏁革細 | 780 |
閭忚集鍏冧欢/鍠厓鏁革細 | 15600 |
RAM 浣嶇附瑷堬細 | 419328 |
杓稿叆/杓稿嚭鏁革細 | 366 |
闆绘簮闆诲锛� | 1.15 V ~ 1.25 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 85°C |
灏佽/澶栨锛� | 672-BBGA |
渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 672-BGA锛�27x27锛� |
鍏跺畠鍚嶇ū锛� | 544-1881 EP2S15F672C5N-ND |
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
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1N4148 | DIODE SGL JUNC 100V 4.0NS DO-35 |
RMC35DRAH-S734 | CONN EDGECARD 70POS .100 R/A PCB |
ECC08DCAH | CONN EDGECARD 16POS R/A .100 SLD |
GCB15DHLN | CONN EDGECARD 30POS .050 DIP SLD |
GBM18DCWT | CONN EDGECARD 36POS DIP .156 SLD |
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁� |
鍙冩暩鎻忚堪 |
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EP2S15F672I4 | 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix II 780 LABs 366 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S15F672I4N | 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix II 780 LABs 366 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S180 | 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet |
EP2S180F1020C3 | 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix II 8970 LABs 742 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S180F1020C3GA | 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix |