7–22
Altera Corporation
Stratix II Device Handbook, Volume 2
January 2008
Fast Passive Parallel Configuration
Figure 7–6. FPP Configuration Timing Waveform
(1)
This timing waveform should be used when the decompression and design security feature are not used.
(2)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE
are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(3)
Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.
(4)
Upon power-up, before and during configuration, CONF_DONE is low.
(5)
DCLK
should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
(6)
DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the
dual-purpose pin settings.
Table 7–9 defines the timing parameters for Stratix II and Stratix II GX
devices for FPP configuration when the decompression and the design
security features are not enabled.
nCONFIG
nSTATUS (3)
CONF_DONE (4)
DCLK
DATA[7..0]
User I/O
INIT_DONE
Byte 0 Byte 1 Byte 2 Byte 3
Byte n
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCH tCL
tDH
tDSU
tCF2CK
tSTATUS
tCLK
tCF2ST0
tST2CK
High-Z
User Mode
(5)
User Mode
Table 7–9. FPP Timing Parameters for Stratix II and Stratix II GX Devices (Part 1 of 2)
Symbol
Parameter
Min
Max
Units
tCF2CD
nCONFIG
low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG
low to nSTATUS low
800
ns
tCFG
nCONFIG
low pulse width
2
s
tSTATUS
nSTATUS
low pulse width
10
s
tCF2ST1
nCONFIG
high to nSTATUS high
s
tCF2CK
nCONFIG
high to first rising edge on DCLK
100
s
tST2CK
nSTATUS
high to first rising edge of DCLK
2
s
