
11–36
Altera Corporation
Stratix Device Handbook, Volume 2
July 2005
Configuration Schemes
Table 11–10 defines the Stratix and Stratix GX timing parameters for PPA
configuration
f
For information on how to create configuration and programming files
for this configuration scheme, see the Software Settings section in the
Configuration Handbook, Volume 2.
JTAG Programming & Configuration
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on printed circuit boards (PCBs) with tight lead spacing.
The BST architecture can test pin connections without using physical test
Table 11–10. PPA Timing Parameters for Stratix & Stratix GX Devices
Symbol
Parameter
Min
Max
Units
tCF2WS
nCONFIG
high to first rising edge on nWS
40
s
tDSU
Data setup time before rising edge on nWS
10
ns
tDH
Data hold time after rising edge on nWS
0ns
tCSSU
Chip select setup time before rising edge on nWS
10
ns
tCSH
Chip select hold time after rising edge on nWS
0ns
tWSP
nWS
low pulse width
15
ns
tCFG
nCONFIG
low pulse width
40
s
tWS2B
nWS
rising edge to RDYnBSY low
20
ns
tBUSY
RDYnBSY
low pulse width
745
ns
tRDY2WS
RDYnBSY
rising edge to nWS rising edge
15
ns
tWS2RS
nWS
rising edge to nRS falling edge
15
ns
tRS2WS
nRS
rising edge to nWS rising edge
15
ns
tRSD7
nRS
falling edge to DATA7 valid with RDYnBSY signal
20
ns
tCD2UM
CONF_DONE
620
s
tSTATUS
nSTATUS
low pulse width
10
s
tCF2CD
nCONFIG
low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG
low to nSTATUS low
800
ns
tCF2ST1
nCONFIG
high to nSTATUS high
s
(1)
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
(2)
This value is obtained if you do not delay configuration by extending the nstatus to low pulse width.