
Altera Corporation
6–17
July 2005
Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Each row block provides 18 bits of data to the multiplier (i.e., one of the
operands to the multiplier), which are routed through the 30 local
interconnects within each DSP row interface block. Any signal in the
device can be the source of the 18-bit multiplier data, by connecting to the
local row interconnect through any row or column.
Each control signal routes through one of the eight rows of the DSP block.
Table 6–4 shows the 18 control signals and the row to which each one
routes.
Input/Output Data Interface Routing
The 30 local interconnects generate the 18 inputs to the row interface
blocks. The 21 outputs of the row interface block are the inputs to the DSP
Table 6–4. Control Signals in DSP Block
Signal Name
Row
Description
signa
1
DSP block-wide signed and unsigned control signals for all multipliers.
The multiplier outputs are unsigned only if both signa and signb are
low.
signb
6
addnsub1
3
Controls addition or subtraction of the two one-level adders. The
addnsub0
signal controls the top two one-level adders; the addnsub1
signal controls the bottom two one-level adders. A high indicates
addition; a low indicates subtraction.
addnsub3
7
accum_sload0
2
Resets the feedback input to the accumulator. The signal
asynchronously clears the accumulator and allows new accumulation to
begin without losing any clock cycles. The accum_sload0 controls the
top two one-level adders, and the accum_sload1 controls the bottom
two one-level adders. A low is for normal accumulation operations and
a high is for zeroing the accumulator.
accum_sload1
7
clock0
3
DSP block-wide clock signals.
clock1
4
clock2
5
clock3
6
aclr0
1
DSP block-wide clear signals.
aclr1
4
aclr2
5
aclr3
7
ena[3..0]
Same rows as the
Clock Signals
DSP block-wide clock enable signals.