Altera
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1S60F1020C7N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 109/864闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC STRATIX FPGA 60K LE 1020-FBGA
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Three Reasons to Use FPGA's in Industrial Designs
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Package Height Change 03/March/2008
妯欐簴鍖呰锛� 8
绯诲垪锛� Stratix®
LAB/CLB鏁�(sh霉)锛� 5712
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 57120
RAM 浣嶇附瑷堬細 5215104
杓稿叆/杓稿嚭鏁�(sh霉)锛� 773
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1020-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1020-FBGA锛�33x33锛�
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Altera Corporation
4鈥�17
January 2006
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Power
Consumption
Altera offers two ways to calculate power for a design: the Altera web
power calculator and the PowerGaugeTM feature in the Quartus II
software.
The interactive power calculator on the Altera web site is typically used
prior to designing the FPGA in order to get a magnitude estimate of the
device power. The Quartus II software PowerGauge feature allows you to
apply test vectors against your design for more accurate power
consumption modeling.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
Stratix devices require a certain amount of power-up current to
successfully power up because of the small process geometry on which
they are fabricated.
Table 4鈥�34 shows the maximum power-up current (ICCINT) required to
power a Stratix device. This specification is for commercial operating
conditions. Measurements were performed with an isolated Stratix
device on the board to characterize the power-up current of an isolated
Table 4鈥�33. Stratix Device Capacitance Note (5)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
CIOTB
Input capacitance on I/O pins in I/O banks
3, 4, 7, and 8.
11.5
pF
CIOLR
Input capacitance on I/O pins in I/O banks
1, 2, 5, and 6, including high-speed
differential receiver and transmitter pins.
8.2
pF
CCLKTB
Input capacitance on top/bottom clock input
pins: CLK[4:7] and CLK[12:15].
11.5
pF
CCLKLR
Input capacitance on left/right clock inputs:
CLK1
, CLK3, CLK8, CLK10.
7.8
pF
CCLKLR+
Input capacitance on left/right clock inputs:
CLK0
, CLK2, CLK9, and CLK11.
4.4
pF
Notes to Tables 4鈥�10 through 4鈥�33:
(1)
When tx_outclock port of altlvds_tx megafunction is 717 MHz, VOD(min) = 235 mV on the output clock pin.
(2)
Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
(3)
Drive strength is programmable according to the values shown in the Stratix Architecture chapter of the Stratix
Device Handbook, Volume 1.
(4)
VREF specifies the center point of the switching range.
(5)
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within 卤0.5 pF.
(6)
VIO and VCM have multiple ranges and values for J=1 through 10.
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
EP1S60F1020I6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1020I6N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1508C5ES 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:Stratix Device Family Data Sheet
EP1S60F1508C6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 1022 IO RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1508C6ES 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:Stratix Device Family Data Sheet