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參數(shù)資料
| 型號： | EM78P451 |
| 英文描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | 8位微控制器的通用產(chǎn)品[英文] |
| 文件頁數(shù)： | 6/52頁 |
| 文件大?。?/td> | 1287K |
| 代理商： | EM78P451 |
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EM78P451
OTP ROM
This specification is subject to change without prior notice.
2002/03/01
14
Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared in
software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is
stopped, and the controller enters the SLEEP2 mode) on the high-to-low transition and is enabled
(the controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the
stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately
18 ms (oscillator start-up timer (OST)) before the next program instruction is executed. The OST is
always activated by wake-up from sleep mode whether the Code Option bit ENWDT is "0" or not.
After waking up, the WDT is enabled if Code Option ENWDT is "1". The block diagram of SLEEP2
mode and wake-up caused by input triggered is depicted in Fig. 5. The SLPC bit can be read and
written.
Bit 5 (WDTE) Control bit used to enable Watchdog timer.
The WDTE bit can be used only if ENWDT, the CODE Option bit, is "1". If the ENWDT bit is "1", then
WDT can be disabled/enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "0". That is, if the ENWDT bit
is "0", WDT is always disabled no matter what the WDTE bit is.
The WDTE bit can be read and written.
Bit 6 (ODE) Open-drain control bit.
0: Both P76 and P77 are normally I/O pins.
1: Both P76 and P77 pins have the open-drain function inside.
The ODE bit can be read and written.
Bits 1~2, and 7 Not used.
7. IOCF (Interrupt Mask Register)
7
6
5
4
3
2
1
0
-
TM1IE
SPIIE
EXIE
TCIE
Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
Bit 1 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
Bit 2 (SPIIE) SPI interrupt enable bit.
0: disable SPI interrupt
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