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參數(shù)資料
| 型號： | EM78P451 |
| 英文描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | 8位微控制器的通用產(chǎn)品[英文] |
| 文件頁數(shù)： | 3/52頁 |
| 文件大?。?/td> | 1287K |
| 代理商： | EM78P451 |
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EM78P451
OTP ROM
This specification is subject to change without prior notice.
2002/03/01
11
0= Disable SPI mode
SRO (bit 5): SPI Read Overflow bit
1 = A new data is received while the previous data is still being held in the SPIB register. In this
situation, the data in SPIS register will be destroyed. To avoid setting this bit, users had better read
SPIRB register even if only the transmission is implemented.
0 = No overflow.
<Note>:
This can only occur in slave mode.
SSE (bit 4): SPI Shift Enable bit
1 = Start to shift, and keep on 1 while the current byte is still being transmitted.
0 = Reset as soon as the shifting is complete, and the next byte is ready to shift.
<Note>: This bit will reset to 0 at every one-byte transmission by the hardware
SBRS (bit 2~bit 0): SPI Baud Rate Select bits
SPI baud rate table is illustrated in SPI section in later pages.
12. RE (TMR1: Timer1 register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0X0E
TMR1/RE TMR17
TMR16
TMR15
TMR14
TMR13
TMR12
TMR11 TMR10
TMR17~TMR10 is bit set of timer1 register and it increases until the value matches PWP and then,
it resets to 0.
13. RF (PWP: Pulse width preset register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0F
PWP/RF
PWP7
PWP6
PWP5
PWP4
PWP3
PWP2
PWP1
PWP0
PWP7~PWP0 is bit set of pulse width preset in advance for the desired width of baud clock.
14. R20~R3E (General Purpose Register)
RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
15. R3F (Interrupt Status Register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x3F
ISR/R3F
-
TM1IF
SPIIF
EXIF
TCIF
Bit 0 (TCIF) the flag of the TCC overflow interrupt. Set as TCC overflow; flag cleared by software.
Bit 1 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software
Bit 2 (SPIIF) SPI interrupt flag. Set by data transmission complete, flag cleared by software.
Bit 3 (TM1IF) Timer1 interrupt flag. Set by the comparator at Timer1 application, flag cleared by
software.
Bits 2~7 are not used and read as “0”.
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