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參數(shù)資料
| 型號： | EM78P451 |
| 英文描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | 8位微控制器的通用產(chǎn)品[英文] |
| 文件頁數(shù)： | 50/52頁 |
| 文件大?。?/td> | 1287K |
| 代理商： | EM78P451 |
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EM78P451
OTP ROM
This specification is subject to change without prior notice.
2002/03/01
7
Generates 4K
× 13 on-chip ROM addresses to the relative programming instruction codes. One
program page is 1024 words long.
All the R2 bits are set to "1"s as a RESET condition occurs.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows
jump to any location on one page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
"MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of PC, and the
ninth and tenth bits (A8~A9) of PC are cleared.
"ADD R2, A" allows a relative address be added to the current PC, and the ninth and tenth bits of PC
are cleared.
Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",
) (except "TBL")
will cause the ninth and tenth bits (A8~A9) of PC to be cleared. Thus, the computed jump is limited
to the first 256 locations of any program page.
"TBL" allows a relative address be added to the current PC (R2+A
→R2), and contents of the ninth
and tenth bits (A8~A9) of PC are not changed. Thus, the computed jump can be on the second (or
third, 4th) 256 locations on one program page.
In case of EM78P451, the most significant bits (A10~A11) will be loaded with the contents of bits
PS0~PS1 in the status register (R3) upon the execution of a "JMP", "CALL", or any other
instructions which writes to R2.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents R2. Such instruction will need one more instruction cycle.
PC
A11A10
A9A8
A7
~
A0
CALL
RET
RETL
RETI
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
000
3FF
Page 0
00
400
7FF
Page 1
800
BFF
Page 2
C00
FFF
Page 3
01
10
11
001:Hareware interrupt location
002:Software interrupt (INT instruction) location
FFF:Reset location
Fig. 3 Program Counter Organization
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