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參數(shù)資料
| 型號： | EM78P451 |
| 英文描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | 8位微控制器的通用產(chǎn)品[英文] |
| 文件頁數(shù)： | 17/52頁 |
| 文件大小： | 1287K |
| 代理商： | EM78P451 |
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EM78P451
OTP ROM
This specification is subject to change without prior notice.
2002/03/01
24
4. Programmed the related registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2 and Table 3.
Table 2 Related Control Registers of the SPI Mode
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0D
*SPIC/RD
CES
SPIE
SRO
SSE
--
SBR2
SBR1
SBR0
0x0F
INTC/IOCF
--
TM1IE
SPIIE
EXIE
TCIE
SPIC: SPI Control Register.
CES (bit 7): Clock Edge Select bit
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level.
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level.
SPIE (bit 6):SPI Enable bit
1 = Enable SPI mode
0 = Disable SPI mode
SRO (bit 5):SPI Read Overflow bit
1 = A new data is received while the previous data is still being on hold in the SPIB register. Under
this condition, the data in SPIS register will be destroyed. To avoid setting this bit, users should read
the SPIRB register even if the transmission is implemented only.
0 = No overflow.
<Note>:This can only occur under slave mode.
SSE (bit 4):SPI Shift Enable bit
1 = Start to shift, and stays on 1 while the current byte continues to transmit.
0 = Reset as soon as the shifting is completed and the next byte is ready to shift.
<Note>:
This bit can be reset by hardware only.
SBRS (bit 2~0): SPI Baud Rate Select Bits
SBRS2 (Bit 2)
SBRS1 (Bit 1)
SBRS0 (Bit 0)
Mode
Baud Rate
0
Master
Fsco/2
0
1
Master
Fsco/4
0
1
0
Master
Fsco/8
0
1
Master
Fsco/16
1
0
Master
Fsco/32
1
0
1
Slave
/SS enable
1
0
Slave
/SS disable
1
Master
TMR1/2
<Note>
In master mode, /SS is disable.
INTC: Interrupt control register
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